DATE: 12-1:30PM on March 24, 2016
LOCATION: E1-06-05 (Engineering Blk E1, Faculty of Engineering, NUS) @ NUS campus (map)
TITLE: A case for fine-grain processor arrays for efficient and high-performance computation
ABSTRACT
The continually-growing number of devices available per chip assures the presence of many processing blocks per die communicating by some type of inter-processor interconnect. It is interesting to consider what the granularity of the processing blocks should be given a fixed amount of die area. Between the domains of FPGAs and traditional processors lies a lightly-explored regime which we call fine-grain many-core, whose processors: can be programmed by simple C programs; typically operate with high throughput and high energy-efficiency; are well suited for deep submicron fabrication technologies; and are well matched to many DSP, multimedia, and embedded workloads, and—somewhat counterintuitively—also to some enterprise and scientific kernels.
The AsAP architecture is a fine-grain many-core system composed of a large number of programmable reduced-complexity processing elements with virtually no algorithm-specific hardware and with individual digitally-tunable clock oscillators operating completely independently with respect to each other (GALS). Oscillators fully halt when there is no work to do, and restart at full speed in less than one cycle after work becomes available. Processors communicate through a reconfigurable full-rate circuit-switched mesh network and the third generation design includes a complementary very-small-area packet router.
An overview will be given of a fully-functional 36-processor chip and a 167-processor 1.2 GHz 65 nm chip with per-core dynamic supply voltage and dynamic clock frequency capabilities. Due to the MIMD architecture and individual near-optimal oscillator halting, the system operates with an energy per operation of 9.2 W at 1 trillion instructions/sec virtually independent of the system load. Several dozen kernels and applications have been coded with power, throughput, and area results comparing very well with solutions on available programmable processors. A simple C compiler and automatic mapping tool greatly simplify programming. A sneak preview of a third generation deep-submicron chip now being tested concludes the talk.
SHORT BIO
Bevan Baas received M.S. and Ph.D. degrees in electrical engineering from Stanford University in 1990 and 1999 respectively. After graduation, he joined Atheros Communications as the second full-time employee after the founders and served as a core member of the team which developed the first IEEE 802.11a Wi-Fi solution. In 2003, he joined the Department of Electrical and Computer Engineering at the University of California, Davis where he is now a Professor.
Dr. Baas was an NSF Fellow from 1990-93 and a NASA GSR Fellow from 1993-96. He received the National Science Foundation CAREER award in 2006, the Best Paper Award at the IEEE Intl Conference on Computer Design in 2011, Best Student Paper Award 3rd place at IEEE Intl MSCS 2015 and IEEE Asilomar 2014, “WACIest” Best-In-Session Paper at DAC 2010, several Best Paper nominations, and he supervised the research that earned the College of Engineering Best Doctoral Dissertation Award Honorable Mention in 2013. From 2007-2012 he was an Associate Editor for the IEEE Journal of Solid-State Circuits. He has Co-Chaired and served on numerous conference program committees and has served as Guest Editor of several special issues.