{"id":30,"date":"2021-11-25T08:52:41","date_gmt":"2021-11-25T08:52:41","guid":{"rendered":"http:\/\/box5801.temp.domains\/~greenico\/?page_id=30"},"modified":"2024-04-08T03:13:17","modified_gmt":"2024-04-08T03:13:17","slug":"publications","status":"publish","type":"page","link":"https:\/\/www.green-ic.org\/publications\/","title":{"rendered":"Publications"},"content":{"rendered":"\t\t<div data-elementor-type=\"wp-page\" data-elementor-id=\"30\" class=\"elementor elementor-30\">\n\t\t\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-5ea68432 elementor-section-boxed elementor-section-height-default elementor-section-height-default\" data-id=\"5ea68432\" data-element_type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-4179570c\" data-id=\"4179570c\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t<div class=\"elementor-element elementor-element-16bbad63 elementor-widget elementor-widget-text-editor\" data-id=\"16bbad63\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t<p><\/p>\n<p><strong>Editorials<\/strong><\/p>\n<p><\/p>\n<p>M. Alioto, \u201cOpening of the 2023 Editorial Year \u2013 This Coda as Prelude of Next TVLSI Cycle with Sustained Growth,\u201d IEEE Trans. on VLSI Systems, vol. 31, no. 1, pp. 1-2, Jan. 2023 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9998455\/\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>)<\/p>\n<p>M. Alioto, \u201cEditorial on the Opening of the 2022 TVLSI Editorial Year \u2013 Connecting Trends from Society to VLSI Systems,<em>\u201d<\/em> IEEE Trans. on VLSI Systems, vol. 30, no. 1, pp. 1-2, Jan. 2022 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9686553\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>)<\/p>\n<p>M. Alioto, \u201cSecond Quarter of the 2021 Editorial Year\u2014A Year in Crescendo,\u201d IEEE Trans. on VLSI Systems, vol. 29, no. 5, pp. 815-842, May 2021 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9416720\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>)<\/p>\n<p><\/p>\n<p>M. Alioto, \u201cOpening of the 2021 Editorial Year \u2013 Overture for a New Year of Change,\u201d IEEE Trans. on VLSI Systems, vol. 29, no. 1, pp. 1-2, Jan. 2021 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9311901\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>)<\/p>\n<p><\/p>\n<p>M. Alioto, \u201cEditorial on the Conclusion of the 2020 Editorial Year \u2013 The Climactic Finale of a Peculiar Year,\u201d IEEE Trans. on VLSI Systems, vol. 28, no. 12, pp. 1-2, Dec. 2020 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9271965\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>)<\/p>\n<p><\/p>\n<p>M. Alioto, \u201cEditorial on the Opening of the New Editorial Year – The State of the Transactions on VLSI Systems,\u201d IEEE Trans. on VLSI Systems, vol. 28, no. 1, pp. 1-2, Jan. 2020 (<a href=\"https:\/\/www.computer.org\/csdl\/journal\/si\/2020\/01\/08945475\/1gbtZxspGUM\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>)<\/p>\n<p><\/p>\n<p>M. Alioto, \u201cEditorial: TVLSI Keynote Papers Enriching Our Transactions with Invited Contributions,\u201d IEEE Trans. on VLSI Systems, vol. 27, no. 7, p. 1485, July 2019 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8746759\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>)<\/p>\n<p><\/p>\n<p>M. Alioto, \u201cEditorial on TVLSI Positioning\u2014Continuing and Accelerating an Upward Trajectory,\u201d IEEE Trans. on VLSI Systems, vol. 27, no. 2, pp. 253-280, Feb. 2019 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8629340\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>)<\/p>\n<p><\/p>\n<p>M. Alioto, V. De, A. Marongiu, Guest Editorial for the Special Issue on \u201cEnergy-Quality Scalable Circuits and Systems for Sensing and Computing: from Approximate, to Communication-Inspired and Learning-Based\u201d, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 8, no. 3, pp. 361-368, Sept. 2018 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8438541\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>)<\/p>\n<p><\/p>\n<p>G. Di Capua, N. Horta, F. Fernandez, G. Dundar, S. Pennisi, G. Palumbo, M. Alioto, G. Giustolisi, Guest Editorial for the Special Issue on Guest Editorial Special Issue on Selected Papers from PRIME 2017 and SMACD 2017, Elsevier INTEGRATION \u2013 The VLSI Journal, vol. 63, pp. 273-274, 2018\u00a0<\/p>\n<p><\/p>\n<p>M. Alioto, E. Sanchez-Sinencio, A. Sangiovanni-Vincentelli, Guest Editorial for the Special Issue on Circuits and Systems for the Internet of Things \u2013 From Sensing to Sensemaking, IEEE Trans. on Circuits and Systems \u2013 part I, vol. 64, no. 9, pp. 2221-2225, Sept. 2017 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8017696\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>)<\/p>\n<p><\/p>\n<p>K. Chakrabarti, M. Alioto, Editorial on the First TVLSI Best AE and Reviewer Awards, IEEE Trans. on VLSI Systems, Aug. 2016 M. Alioto, Guest Editorial for the Special Issue on Ultra-Low-Voltage VLSI Circuits and Systems for Green Computing, IEEE Trans. on VLSI Systems, Aug. 2016 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/6401178\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>)<\/p>\n<p>M. Alioto,\u00a0Guest Editorial for the Special Issue on Ultra-Low-Voltage VLSI Circuits and Systems for Green Computing, IEEE Trans. on Circuits and Systems \u2013 part II, vol. 59, no. 12, pp. 849-852, Dec. 2012 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/6401178\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>)<\/p>\n<p><\/p>\n<p>\u00a0<\/p>\n<p><strong>Books or book chapters<\/strong><\/p>\n<p><\/p>\n<p>L. Lin, S. Jain, K. Ali Ahmed, M. Alioto, <em>Self-Powered Sensors for Next-Gen IoT – Everywhere, Always-on and Green<\/em>, Springer, 2023 (Springer, Scholar Bank draft)<\/p>\n<p>S. Taneja, M. Alioto, <em>Immersed-in-Logic and In-Memory Primitives for Ubiquitous Hardware Security<\/em>, Springer, 2023 (Springer, Scholar Bank draft)<\/p>\n<p>S. Jain, L. Lin, M. Alioto,\u00a0<em>Adaptive Digital Circuits for Power-Performance Range beyond Wide Voltage Scaling<\/em>, Springer, 2020 (<a href=\"https:\/\/link.springer.com\/book\/10.1007\/978-3-030-38796-9\">Springer<\/a>, <a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/189440\" target=\"_blank\" rel=\"noopener\">Scholar Bank draft<\/a>)<\/p>\n<p><\/p>\n<p>M. Alioto (Ed.),\u00a0<em>Enabling the Internet of Things – from Integrated Circuits to Integrated Systems<\/em>, Springer, 2017 (<a href=\"https:\/\/link.springer.com\/book\/10.1007\/978-3-319-51482-6\" target=\"_blank\" rel=\"noopener\">Springer<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>M. Alioto, E. Consoli, G. Palumbo,\u00a0<em>Flip-Flop Design in Nanometer CMOS – from High Speed to Low Energy<\/em>, Springer, 2015 (<a href=\"https:\/\/link.springer.com\/book\/10.1007\/978-3-319-01997-0\" target=\"_blank\" rel=\"noopener\">Springer<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>M. Alioto, E. Consoli, G. Palumbo, \u201cDesign in the Energy-Delay Space,\u201d (Chapter1) in Advanced Circuits for Emerging Technologies, Part I – Digital Design and Power Management, Wiley, March 2012 (<a href=\"https:\/\/link.springer.com\/chapter\/10.1007\/978-3-319-01997-0_2\" target=\"_blank\" rel=\"noopener\">Springer<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>M. Alioto, G. Palumbo,\u00a0<em>Model and Design of Bipolar and MOS Current-Mode Logic (CML, ECL and SCL Digital Circuits)<\/em>, New York, Springer, 2005 (<a href=\"https:\/\/link.springer.com\/book\/10.1007\/1-4020-2888-1\" target=\"_blank\" rel=\"noopener\">Springer<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>\u00a0<\/p>\n<p><strong>International journals (2006-today)<\/strong><\/p>\n<p>J. Basu, L. Fassio, K. Ali, M. Alioto, \u201cPicowatt-Power Super-Cutoff Analog Building Blocks and 78-pW Battery-Less Wake-Up Receiver for Light-Harvested Near-Always-On Operation,\u201d accepted to IEEE Journal of Solid-State Circuits (invited), Jan. 2024 (IEEE manuscript, Scholar Bank draft)<\/p>\n<p>H. Zhang, L. Lin, Q. Fang, M. Alioto, \u201cLaser Voltage Probing Attack Detection with 100% Area\/Time Coverage at Above\/Below the Bandgap Wavelength and Fully-Automated Design\u201d accepted to IEEE Journal of Solid-State Circuits (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/10136181\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0<a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/231063\" target=\"_blank\" rel=\"noopener\">Scholar Bank draft<\/a>)<\/p>\n<p>O. Aiello, P. Crovetti, M. Alioto, \u201cCapacitance-to-Digital Converter for Harvested Systems Down to 0.3 V With No Trimming, Reference, and Voltage Regulation,\u201d IEEE Trans. on Circuits and Systems \u2013 part I, vol. 70, no. 4, pp. 1439-1449, April 2023 (<a href=\"https:\/\/ieeexplore.ieee.org\/abstract\/document\/10026247\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0<a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/216938\" target=\"_blank\" rel=\"noopener\">Scholar Bank draft<\/a>)<\/p>\n<p>K. Ali, J. H. Teo, S. Sarkar, M. Alioto, \u201cDual-Mode Conversion Gating, Comparator Merging and Reference-Less Calibration for 2.7X Energy Reduction in SAR ADCs under Low-Activity Inputs,\u201d in print on IEEE Solid-State Circuits Letters (<a href=\"https:\/\/ieeexplore.ieee.org\/abstract\/document\/10048489\">IEEE manuscript<\/a>, Scholar Bank draft)<\/p>\n<p>L. Fassio, L. Lin, R. De Rose, M. Lanuzza, F. Crupi, M. Alioto, \u201cVoltage Reference with Corner-Aware Replica Selection\/Merging for 1.4-mV Accuracy in Harvested Systems down to 3.9 pW, 0.2 V,\u201d in print on IEEE Access (<a href=\"https:\/\/ieeexplore.ieee.org\/stamp\/stamp.jsp?arnumber=10007824\">IEEE manuscript<\/a>, <a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/237225\">Scholar Bank draft<\/a>)<\/p>\n<p>M. Alioto, \u201cAggressive Design Reuse for Ubiquitous Zero-Trust Edge Security \u2013 From Physical Design to Machine Learning-Based Hardware Patching,\u201d in print on IEEE Open Journal of the Solid-State Circuits Society\u00a0(<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9955388\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>, Scholar Bank draft)<\/p>\n<p>T.-N. Pham, Q.-K. Trinh, I.-J. Chang, M. Alioto, \u201cSTT-BNN: A Novel STT-MRAM In-Memory Computing Macro for Binary Neural Networks,\u201d accepted to IEEE JETCAS (<span style=\"font-size: 11pt; font-family: Calibri, sans-serif;\"><a href=\"https:\/\/ieeexplore.ieee.org\/document\/9762321\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft<\/span>)<\/p>\n<p><span style=\"font-family: var( --e-global-typography-text-font-family ), Sans-serif; font-weight: var( --e-global-typography-text-font-weight );\">S. Taneja, V. Konandur Rajanna, M. Alioto, \u201cIn-Memory Unified TRNG and Multi-Bit PUF for Ubiquitous Hardware Security,\u201d IEEE Journal of Solid-State Circuits (invited), vol. 57, no. 1, pp. 153-166, Jan. 2022 <\/span><span style=\"color: var( --e-global-color-text ); text-align: justify; font-family: Tahoma, sans-serif;\"><span style=\"font-size: 11pt; font-family: Calibri, sans-serif;\">(<\/span><\/span><span style=\"font-weight: var( --e-global-typography-text-font-weight ); font-size: 11pt; font-family: Calibri, sans-serif;\"><a href=\"https:\/\/ieeexplore.ieee.org\/document\/9664399\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a><\/span><span style=\"font-weight: var( --e-global-typography-text-font-weight ); font-size: 11pt; font-family: Calibri, sans-serif;\">,\u00a0<\/span><span style=\"font-weight: var( --e-global-typography-text-font-weight ); font-size: 11pt; font-family: Calibri, sans-serif;\"><a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/191224\" target=\"_blank\" rel=\"noopener\">Scholar Bank draft<\/a><\/span><span style=\"color: var( --e-global-color-text ); text-align: justify; font-family: Tahoma, sans-serif;\"><span style=\"font-size: 11pt; font-family: Calibri, sans-serif;\">)<\/span><\/span><\/p>\n<p><\/p>\n<p>U. De Alwis, M. Alioto, \u201cTempDiff: Feature Map-Level CNN Sparsity Enhancement at Near-Zero Memory Overhead via Temporal Difference,\u201d IEEE JETCAS, vol. 11, no. 4, pp. 620-633, Dec. 2021 (<span style=\"font-size: 11pt; font-family: Calibri, sans-serif;\"><a href=\"https:\/\/ieeexplore.ieee.org\/document\/9615040\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0<a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/237226\">Scholar Bank draf<\/a>t<\/span>)<\/p>\n<div><span style=\"font-family: var( --e-global-typography-text-font-family ), Sans-serif; font-weight: var( --e-global-typography-text-font-weight );\">V. Konandur Rajanna, M. Alioto, \u201cOn-Chip Links with Energy-Quality Tradeoff in Error-Resilient and Machine Learning Applications,\u201d IEEE Journal of Solid-State Circuits, vol. 56, no. 11, pp. 3533-3543, Nov. 2021 (<\/span><a style=\"font-family: var( --e-global-typography-text-font-family ), Sans-serif; font-weight: var( --e-global-typography-text-font-weight ); background-color: #ffffff;\" href=\"https:\/\/ieeexplore.ieee.org\/document\/9492044\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a><span style=\"font-family: var( --e-global-typography-text-font-family ), Sans-serif; font-weight: var( --e-global-typography-text-font-weight );\">,\u00a0<a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/192293\" target=\"_blank\" rel=\"noopener\">Scholar Bank draft<\/a>)<\/span><\/div>\n<p><\/p>\n<p>S. Jain, L. Lin, M. Alioto, \u201c\u00b1CIM SRAM for Signed In-Memory Broad-Purpose Computing from DSP to Neural Processing,\u201d IEEE Journal of Solid-State Circuits (invited), vol. 56, no. 10, pp. 2981-2992, Oct 2021 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9481107\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>P. Toledo, P. Crovetti, O. Aiello, M. Alioto, \u201cDesign of Digital OTAs with Operation down to 0.3 V and nW Power for Direct Harvesting,\u201d\u00a0IEEE Trans. On Circuits and Systems \u2013 part I, vol. 68, no. 9, pp. 3693-3706, Sept. 2021 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9464792\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>S. Taneja, M. Alioto, \u201cFully-Synthesizable Unified True Random Number Generator and Cryptographic Core,\u201d IEEE Journal of Solid-State Circuits (invited), vol. 56, no. 10, pp. 3049-3061, Oct. 2021 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9531601\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0<a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/199929\" target=\"_blank\" rel=\"noopener\">Scholar Bank draft<\/a>)<\/p>\n<p><\/p>\n<p>P. Toledo, P. Crovetti, H. Klimach, S. Bampi, O. Aiello, M. Alioto, \u201cA 300mV-Supply, sub-nW Power Digital-Based Operational Transconductance Amplifier,\u201d IEEE Trans. on Circuits and Systems \u2013 part II, vol. 68, no. 9, pp. 3073-3077, Sept. 2021 (<a href=\"http:\/\/ieeexplore.ieee.org\/document\/9442808\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>L. Fassio, L. Lin, R. De Rose, M. Lanuzza, F. Crupi, M. Alioto, \u201cA 0.6-to-1.8V Trimming-Less CMOS Current Reference with Near-100% Power Utilization,\u201d IEEE Trans. on Circuits and Systems \u2013 part II, vol. 68, no. 9, pp. 3038-3042, Sept. 2021 (<a href=\"https:\/\/ieeexplore.ieee.org\/stamp\/stamp.jsp?arnumber=9916267\">IEEE manuscript<\/a>, <a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/191973\">Scholar Bank draft<\/a>)<\/p>\n<p><\/p>\n<p>L. Fassio, L. Lin, R. De Rose, M. Lanuzza, F. Crupi, M. Alioto, \u201cTrimming-Less Voltage Reference for Highly-Uncertain Harvesting down to 0.25V, 5.4-pW,\u201d IEEE Journal of Solid-State Circuits, vol. 56, no. 10, pp. 3134-3144, Oct. 2021 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9443081\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0<a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/237221\">Scholar Bank draft<\/a>)<\/p>\n<p><\/p>\n<p>M. Alioto, \u201cFrom Less Batteries to Battery-Less Integrated Systems through Ultra-Wide Power-Performance Adaptation down to pWs,\u201d IEEE Design&Test (invited), vol. 38, no. 5, pp. 90-133, Oct. 2021 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>O. Aiello, P. Crovetti, P. Toledo, M. Alioto, \u201cRail-to-Rail Dynamic Voltage Comparator Scalable down to pW-Range Power and 0.15-V Supply,\u201d\u00a0vol. 68, no. 7, pp. 2675-2679, July 2021 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9353717\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0<a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/189169\" target=\"_blank\" rel=\"noopener\">Scholar Bank draft<\/a>)<\/p>\n<p><\/p>\n<p>S. Taneja, M. Alioto, \u201cPUF Architecture with Run-Time Adaptation for Resilient and Energy-Efficient Key Generation via Sensor Fusion,\u201d\u00a0IEEE Journal of Solid-State Circuits, vol. 56, no. 7, pp. 2182-2192, July 2021 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9367184\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0<a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/191221\" target=\"_blank\" rel=\"noopener\">Scholar Bank draft<\/a>)<\/p>\n<p><\/p>\n<p>L. Lin, S. Jain, M. Alioto, \u201cSub-nW Microcontroller with Dual-Mode Logic and Self-Startup for Battery-Indifferent Sensor Nodes,\u201d\u00a0IEEE Journal of Solid-State Circuits, vol. 56, no. 5, pp. 1618-1629, May 2021 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9272627\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0<a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/189167\" target=\"_blank\" rel=\"noopener\">Scholar Bank draft<\/a>)<\/p>\n<p><\/p>\n<p>P. Toledo, P. Crovetti, O. Aiello, M. Alioto, \u201cFully Digital Rail-to-Rail OTA with Sub-1,000 \u00b5m<sup>2<\/sup>\u00a0Area, 250-mV Minimum Supply and nW Power at 150-pF Load in 180nm,\u201d IEEE Solid-State Circuits Letters, vol. 3, pp. 474-477, Sept. 2020 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9209072\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>S. Jain, L. Lin, M. Alioto, \u201cBroad-Purpose In-Memory Computing for Signal Monitoring and Machine Learning Workloads,\u201d IEEE Solid-State Circuits Letters (invited), vol. 3, pp. 394-397, Sept. 2020 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9199903\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0<a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/189165\" target=\"_blank\" rel=\"noopener\">Scholar Bank draft<\/a>)<\/p>\n<p><\/p>\n<p>S. Taneja, M. Alioto, \u201cFully-Synthesizable All-Digital Unified Dynamic Entropy Generation, Extraction and Utilization within the Same Cryptographic Core,\u201d IEEE Solid-State Circuits Letters (invited), vol. 3, pp. 402-405, Sept. 2020 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9199880\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0<a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/172972\" target=\"_blank\" rel=\"noopener\">Scholar Bank draft<\/a>)<\/p>\n<p><\/p>\n<p>L. Fassio, F. Settino, L. Longyang, R. De Rose, M. Lanuzza, F. Crupi, M. Alioto, \u201cA Robust Sub-Threshold, Low Power-Delay, Energy and Area Efficient Level Shifter,\u201d\u00a0IEEE Trans. on Circuits and Circuits \u2013 part II, vol. 68, no. 4, pp. 1393-1397, April 2021 (<a href=\"https:\/\/ieeexplore.ieee.org\/stamp\/stamp.jsp?arnumber=9160930\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0<a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/189168\">Scholar Bank draft<\/a>)<\/p>\n<p><\/p>\n<p>S. Jain, L. Lin, M. Alioto, \u201cProcessor Energy-Performance Range Extension Beyond Voltage Scaling via Drop-In Methodologies,\u201d IEEE Journal of Solid-State Circuits (invited), vol. 55, no. 10, pp. 2670-2679, Oct. 2020 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9138436\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0<a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/189166\" target=\"_blank\" rel=\"noopener\">Scholar Bank draft<\/a>)<\/p>\n<p><\/p>\n<p>F. Frustaci, S. Perri, P. Corsonello, M. Alioto, \u201cApproximate Multipliers with Dynamic Truncation for Energy Reduction via Graceful Quality Degradation,\u201d IEEE Transactions on Circuits and Systems \u2013 part II, vol. 67, no. 12, pp. 3427-3431, Dec. 2020 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9105108\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>O. Aiello, P. Crovetti, M. Alioto, \u201cFully Synthesizable Low-Area Analogue-to-Digital Converters with Minimal Design Effort Based on the Dyadic Digital Pulse Modulation,\u201d IEEE Access, vol. 8, no. 1, pp. 70890 \u2013 70899, April 2020 (<a href=\"https:\/\/ieeexplore.ieee.org\/abstract\/document\/9062548\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0<a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/183432\" target=\"_blank\" rel=\"noopener\">Scholar Bank draft<\/a>)<\/p>\n<p><\/p>\n<p>A. Alvarez, G. Ponnusamy, M. Alioto, \u201cEnergy-Quality Scalable Memory-Frugal Feature Extraction for Always-On Deep Sub-mW Distributed Vision,\u201d IEEE Access, vol. 8, pp. 18951-18961, Jan. 2020 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8966284\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0<a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/189162\" target=\"_blank\" rel=\"noopener\">Scholar Bank draft<\/a>)<\/p>\n<p><\/p>\n<p>J. H. Teo, S. Cheng, M. Alioto, \u201cLow-Energy Voice Activity Detection via Energy-Quality Scaling from Data Conversion to Machine Learning,\u201d IEEE Trans. on CAS \u2013 part I, vol. 67, no. 4, pp. 1378-1377, April 2020 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8949811\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0<a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/189163\" target=\"_blank\" rel=\"noopener\">Scholar Bank draft<\/a>)<\/p>\n<p><\/p>\n<p>L. Lin, S. Jain, M. Alioto, \u201cIntegrated Power Management for Battery-Indifferent Systems with Ultra-Wide Adaptation down to nW,\u201d IEEE Journal of Solid-State Circuits (invited), vol. 55, no. 4, pp. 967-976, April 2020 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8945241\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>S. Jain, L. Longyang, M. Alioto, \u201cAutomated Design of Reconfigurable Micro-Architectures for Accelerators under Wide Voltage Scaling,\u201d IEEE Trans. on VLSI Systems, vol. 28, no. 3, pp. 777-790, March 2020 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8902149\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>L. Lin, S. Jain, M. Alioto, \u201cReconfigurable Clock Networks for Wide Voltage Scaling,\u201d IEEE Journal of Solid-State Circuits, vol. 54, no. 9, pp. 2622-2631, Sept. 2019 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8765351\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>O. Aiello, P. Crovetti, M. Alioto, \u201cStandard Cell-Based Ultra-Compact DACs in 40nm CMOS,\u201d IEEE Access, vol. 7, no. 1, pp. 126479-126488, Aug. 2019 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8821285\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0<a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/209616\" target=\"_blank\" rel=\"noopener\">Scholar Bank draft<\/a>)<\/p>\n<p><\/p>\n<p>M. Alioto, \u201cTrends in Hardware Security: from Basics to ASICs,” IEEE Solid-State Circuits Magazine (invited), vol. 11, no. 3, pp. 56-74, Aug. 2019 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8811774\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0<a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/191220\" target=\"_blank\" rel=\"noopener\">Scholar Bank draft<\/a>)<\/p>\n<p><\/p>\n<p>O. Aiello, P. Crovetti, M. Alioto, \u201cFully Synthesizable 12-bit, 500um2, 55kS\/s DAC with Graceful Degradation and Dynamic Power-Resolution Scaling in 40nm,\u201d IEEE Trans. on CAS \u2013 part I, vol. 66, no. 8, pp. 2865-2875, Aug. 2019 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>O. Aiello, P. Crovetti, L. Lin, M. Alioto, \u201cA pW-Power Hz-Range Oscillator Operating with a 0.3V-1.8V Unregulated Supply,\u201d IEEE Journal of Solid-State Circuits, vol. 54, no. 5, pp. 1487-1496, May 2019 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8616819\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>F. Frustaci, S. Perri, P. Corsonello, M. Alioto, \u201cEnergy-Quality Scalable Adders Based on Non-Zeroing Bit Truncation,\u201d IEEE Trans. on VLSI Systems, vol. 27, no. 4, pp. 964-968, April 2019 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8561219\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>M. N. Aman, S. Taneja, B. Sikdar, K. C. Chua, M. Alioto, \u201cToken-Based Security for the Internet of Things with Dynamic Energy-Quality Tradeoff,\u201d IEEE Internet of Things Journal, vol. 6, no. 2, pp. 2843-2859, Feb. 2019 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8489899\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)\u00a0<\/p>\n<p><\/p>\n<p>M. Alioto, V. De, A. Marongiu, \u201cEnergy-Quality Scalable Integrated Circuits and Systems: Continuing Energy Scaling in the Twilight of Moore\u2019s Law,\u201d IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 8, no. 4, pp. 653-678, Dec. 2018 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8536377\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>S. Taneja, A. Alvarez, M. Alioto, \u201cFully Synthesizable PUF Featuring Hysteresis and Temperature Compensation for 3.2% Native BER and 1.02fJ\/b in 40nm,\u201d IEEE Journal of Solid-State Circuits (invited), vol. 53, no. 10, pp. 2828-2839, Oct. 2018 (invited) (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8456830\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>Q.-K. Trinh, S. Ruocco, M. Alioto, \u201cTime-Based Sensing for Reference-Less and Robust Read in STT-MRAM Memories,\u201d IEEE Trans. on CAS \u2013 part I, vol. 65, no. 10, pp. 3338-3348, Oct. 2018 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8361484\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>S. Jain, L. Longyang, M. Alioto, \u201cDynamically Adaptable Pipeline for Energy-Efficient Microarchitectures under Wide Voltage Scaling,\u201d IEEE Journal of Solid-State Circuits, vol. 53, no. 2, pp. 632-641, Feb. 2018 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8115158\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>R. De Rose, M. Lanuzza, F. Crupi, G. Siracusano, R. Tomasello, G. Finocchio, M. Carpentieri, M. Alioto, \u201cA Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS\/MTJ Circuits,\u201d IEEE Trans. on CAS \u2013 part I, vo. 65, no. 3, pp. 1086-1095, March 2018 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8090899\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>Q. K. Trinh, S. Ruocco, M. Alioto, \u201cDynamic Reference Voltage Sensing Scheme for Read Margin Improvement in STT-MRAMs,\u201d IEEE Trans. on CAS \u2013 part I, vol. 65, no. 4, pp. 1269-1278, April 2018 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8052158\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>Y. Zhang, M. Khayatzadeh, K. Yang, M. Saligane, N. Pinckney, M Alioto, D. Blaauw, D. Sylvester, \u201ciRazor: Current-Based Error Detection and Correction Scheme for PVT variation in 40-nm ARM Cortex-R4 Processor,\u201d IEEE Journal of Solid-State Circuits, vol. 53, no. 2, pp. 619-631, Feb. 2018 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8060508\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>M. Alioto, M. Shahghasemi, \u201cThe Internet of Things on Its Edge: Trends towards Its Tipping Point,\u201d in print on the special issue on \u201cRecent Advances on IoT-based Consumer Electronics\u201d, IEEE Consumer Electronics Magazine (invited), vol. 7, no. 1, pp. 77-87, Jan. 2018 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8197432\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>S. Jain, L. Lin, M. Alioto, \u201cDesign-Oriented Energy Models for Wide Voltage Scaling down to the Minimum Energy Point,\u201d IEEE Trans. on CAS \u2013 part I, vol. 64, no. 12, pp. 3115-3125, Dec. 2017 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8013083\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>M. Alioto, G. Scotti, A. Trifiletti, \u201cA Novel Framework to Estimate the Path Delay Variability on the Back of an Envelope via the Fan-Out-of-4 Metric,\u201d IEEE Trans. on CAS \u2013 part I, vol. 64, no. 8, pp. 2073-2085, Aug. 2017 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/7894172\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>K. T. Quang, S. Ruocco, M. Alioto, \u201cNovel Boosted-Voltage Sensing Scheme for Variation-Resilient STT-MRAM Read,\u201d IEEE Trans. on CAS \u2013 part I, vol. 63, no. 10, pp. 1652-1660, Oct. 2016 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/7571107\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>F. Frustaci, D. Blaauw, D. Sylvester, M. Alioto, \u201cApproximate SRAMs with Dynamic Energy-Quality Management,\u201d IEEE Trans. on VLSI Systems, vol. 24, no. 6, pp. 2128-2141, June 2016 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/7372479\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>A. Alvarez, W. Zhao, M. Alioto, \u201cStatic Physically Unclonable Functions for Secure Chip Identification with 1.9-5.8% Native Bit Instability at 0.6-1 V and 15 fJ\/bit in 65nm,\u201d IEEE Journal on Solid-State Circuits, vol. 51, no. 3, pp. 763-775, March 2016 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/7397840\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>K. T. Quang, S. Ruocco, M. Alioto, \u201cVoltage Scaled STT-MRAMs towards Minimum-Energy Write Access,\u201d IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 6, no. 3, pp. 305-318, Sept 2016 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/7448480\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>F. Frustaci, M. Khayatzadeh, D. Blaauw, D. Sylvester, M. Alioto, \u201cSRAM for Error-Tolerant Applications with Dynamic Energy-Quality Management in 28nm CMOS,\u201d IEEE Journal of Solid-State Circuits, vol. 50, no. 3, pp. 1310-1323, March 2015 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/7063974\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>M. Alioto, Elio Consoli, G. Palumbo, \u201cVariations in Nanometer CMOS Flip-Flops: Part II \u2013 \u00a0Energy Variability and Impact of Other Sources of Variations,\u201d IEEE Trans. on CAS \u2013 part I, vol. 62, n. 3, pp. 835-843, March 2015 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/7008547\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0<a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/123470?mode=full\" target=\"_blank\" rel=\"noopener\">Scholar Bank draft<\/a>)<\/p>\n<p><\/p>\n<p>M. Alioto, Elio Consoli, G. Palumbo, \u201cVariations in Nanometer CMOS Flip-Flops: Part I \u2013 \u00a0Impact of Process Variations on Timing,\u201d in print on IEEE Trans. on CAS \u2013 part I (<a href=\"https:\/\/ieeexplore.ieee.org\/abstract\/document\/7008531\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>M. Shoaran, A. Tajalli, M. Alioto, A. Schmid, Y. Leblebici, \u201cAnalysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits,\u201d IEEE Trans. on CAS \u2013 part I, vol. 62, no. 2, pp. 458-467, Feb. 2015 (<a href=\"https:\/\/ieeexplore.ieee.org\/abstract\/document\/6954536\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>L. Freyman, D. Fick, M. Alioto, D. Blaauw, D. Sylvester, \u201cA 346\u03bcm2 VCO-based, Reference-Free, Self-Timed Sensor Interface for Cubic-Millimeter Sensor Nodes in 28nm CMOS,\u201d IEEE Journal of Solid-State Circuits, vol. 49, no. 11, pp. 2462-2473, Nov. 2014 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/6917057\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>L. Artola, G. Hubert, M. Alioto, \u201cComparative soft error evaluation of layout cells in FinFET technology,\u201d in print on Microelectronics Reliability (Elsevier) (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>W. Zhao, Y. Ha, M. Alioto, \u201cNovel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study,\u201d in print on IEEE Trans. on VLSI Systems (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/6877700\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>, Scholar Bank draft)<\/p>\n<p><\/p>\n<p>M. Tache, V. Beiu, W. Ibrahim, F. Kharbash, M. Alioto, \u201cEnhancing the Static Noise Margins by Upsizing Length for Ultra-Low Voltage\/Power\/Energy Gates\u201d Journal of Low Power Electronics, Vol. 10, N\u00b0 1, pp. 137-148, March 2014 (invited, special selection on the 4th European Workshop on CMOS Variability – VARI 2013).(IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>M. Alioto, D. Esseni, \u201cTunnel FETs for Ultra-Low Voltage Digital VLSI Circuits: Part II \u2013 Evaluation at Circuit Level and Design Perspectives,\u201d IEEE Trans. on VLSI Systems, vol. 22, no. 12, pp. 2499-2512, Dec. 2014 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/6754164\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>D. Esseni, M. Guglielmini, B. Kapidani, T. Rollo, M. Alioto, \u201cTunnel FETs for Ultra-Low Voltage Digital VLSI Circuits: Part I \u2013 Device-Circuit Interaction and Evaluation at Device Level,\u201d IEEE Trans. on VLSI Systems, vol. 22, no. 12, pp. 2488-2498, Dec. 2014 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/6748988\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>E. Consoli, G. Palumbo, J. Rabaey, M. Alioto, \u201cA Novel Class of Energy-Efficient Very High-Speed Conditional Push-Pull Pulsed Latches,\u201d IEEE Trans. on VLSI Systems, vol. 22, no. 7, pp. 1593-1605, July 2014 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/6594886\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>M. Alioto, S. Bongiovanni, M. Djukanovic, G. Scotti, \u00a0A. Trifiletti, \u201cEffectiveness of Leakage Power Analysis attacks on DPA-resistant logic styles under process variations,\u201d IEEE Trans. on Circuits and Systems \u2013 part I, vol. 61, no. 2, pp. 429-442, Feb. 2014 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/6585802\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>M. Alioto, E. Consoli, J. Rabaey, \u201c\u201cEChO\u201d Reconfigurable Power Management Unit for Energy Reduction in Sleep-Active Transitions,\u201d IEEE Journal of Solid-State Circuits (invited), vol. 48, no. 8, pp. 1921-1932, Aug. 2013 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/6517539\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>F. Crupi, D. Albano, M. Alioto, J. Franco, L. Selmi, J. Mitard, G. Groeseneken, \u201cImpact of High-Mobility Materials on the Performance of Near- and Sub-Threshold CMOS Logic Circuits,\u201d IEEE Transactions on Electron Devices, vol. 60, no. 3, pp. 972-977, March 2013 (<a href=\"https:\/\/ieeexplore.ieee.org\/abstract\/document\/6457444\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>F. Crupi, M. Alioto, J. Franco, P. Magnone, M. Togo, N. Horiguchi, G. Groeseneken, \u201cUnderstanding the Basic Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic from Device Measurements,\u201d IEEE Trans. on Circuits and Systems \u2013 part II, vol. 59, no. 7, pp. 439-442, July 2012 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/6220866\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>M. Alioto, G. Palumbo, M. Pennisi, \u201cA Simple Circuit Approach to Reduce Delay Variations in Domino Logic Gates,\u201d IEEE Trans. on Circuits and Systems \u2013 part I, vol. 59, no. 10, pp. 2292-2300, Oct. 2012 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/6194979\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>F. Crupi, M. Alioto, J. Franco, P. Magnone, B. Kaczer, G. Groeseneken, J. Mitard, L. Witters, T. Y. Hoffmann, \u201cBuried Silicon Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits under Aggressive Voltage Scaling,\u201d IEEE Trans. on VLSI Systems, vol. 20, no. 8, pp. 1487-1495, Aug. 2012 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/5959243\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>D. Baccarin, D. Esseni, M. Alioto, \u201cMixed FBB\/RBB: a Novel Low-Leakage Technique for FinFET Forced Stacks,\u201d IEEE Trans. on VLSI Systems, vol. 20, no. 8, pp. 1467-1472, Aug. 2012 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/5934621\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>F. Frustaci, M. Alioto, P. Corsonello, \u201cTapered-Vth Approach for Energy-Efficient CMOS Buffers,\u201d IEEE Trans. on Circuits and Systems \u2013 part I, vol. 58, no. 11, pp. 2698-2707, Nov. 2011 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/5938006\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>M. Alioto, E. Consoli, G. Palumbo, \u201cFrom Energy-Delay Metrics to Constraints on the Design of Digital Circuits,\u201d International Journal of Circuit Theory and Applications, vol. 40, no. 8,\u00a0 pp. 815-834, Aug. 2012 (<a href=\"http:\/\/onlinelibrary.wiley.com\/doi\/10.1002\/cta.757\/pdf\" target=\"_blank\" rel=\"noopener\">Wiley manuscript<\/a>, Scholar Bank draft)<\/p>\n<p>M. Alioto, \u201cUltra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial,\u201d IEEE Trans. on Circuits and Systems \u2013 part I (invited), vol. 59, no. 1, pp. 3-29, Jan. 2012 (IEEE manuscript,\u00a0<span style=\"color: var( --e-global-color-text ); font-family: var( --e-global-typography-text-font-family ), Sans-serif; font-weight: var( --e-global-typography-text-font-weight );\">Scholar Bank draft)<\/span><\/p>\n<p><\/p>\n<p>M. Alioto, \u201dModeling Strategies of the Input Admittance of RC Interconnects for VLSI CAD Tools,\u201d Microelectronics Journal (Elsevier), vol. 42, no. 1, pp. 63-73, Jan. 2011 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>M. Alioto, M. Poli, G. Palumbo, \u201cOptimized Design of Parallel Carry-Select Adders,\u201d Integration \u2013 the VLSI Journal (Elsevier), vol. 44, no. 1, pp. 62-74, Jan. 2011 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>M. Alioto, S. Badel, Y. Leblebici, \u201cOptimization of the Wire Grid Size for Differential Routing: Analysis and Impact on the Power-Delay-Area Tradeoff,\u201d Microelectronics Journal (Elsevier), vol. 41, no. 10, pp. 669-679, Oct. 2010 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/5117998\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>P. Magnone, F. Crupi, M. Alioto, B. Kaczer, B. De Jaeger, \u201dUnderstanding the Potential and the Limits of Germanium pMOSFETs for VLSI Circuits from Experimental Measurements,\u201d IEEE Trans. on VLSI Systems, vol. 19, no. 9, pp. 1569-1582, Sept. 2011 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/5508322?arnumber=5508322\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>M. Alioto, \u201dComparative Evaluation of Layout Density in 3T, 4T and MT FinFET Standard Cells,\u201d IEEE Trans. on VLSI Systems, vol. 19, no. 5, pp. 751-762, May 2011 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/5419976\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>M. Alioto, E. Consoli, G. Palumbo, \u201cAnalysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II \u2013 Results and Figures of Merit,\u201d IEEE Trans. on VLSI Systems, vol. 19, no. 5, pp. 737-750, May 2011 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/5438835\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>M. Alioto, E. Consoli, G. Palumbo, \u201dAnalysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I – Methodology and Design Strategies,\u201d IEEE Trans. on VLSI Systems, vo. 19, no. 5, pp. 725-736, May 2011 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/5419974\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>M. Alioto, \u201c Understanding DC Behavior of Subthreshold CMOS Logic through Closed-Form Analysis,\u201d IEEE Trans. on Circuits and Systems \u2013 part I, vol. 57, no. 7, pp. 1597-1607, July 2010 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/5395622\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>M. Alioto, E. Consoli, G. Palumbo, \u201cGeneral Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space,\u201d IEEE Trans. on Circuits and Systems \u2013 part I, vol. 57, no. 7, pp. 1583-1596, July 2010 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/5371815\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>M. Alioto, E. Consoli, G. Palumbo, \u201cFlip-Flop Energy\/Performance versus Clock Slope and Impact on the Clock Network Design,\u201d IEEE Trans. on Circuits and Systems \u2013 part I, vol. 57, no. 6, pp. 1273-1286, June 2010 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/5371919\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, \u201cA variability-tolerant feedback technique for throughput maximization of TRBGs with predefined entropy,\u201d Special Issue \u201cAdvances in oscillator analysis and design\u201d of the Journal of Circuits, Systems, and Computers, vol. 19, no. 4, pp. 879-895, 2010 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>M. Alioto, G. Palumbo, M. Poli, \u201cSimple and Accurate Modeling of the Output Transition Time in Nanometer CMOS Gates,\u201d International Journal of Circuit Theory and Applications, vol. 38, no. 10, pp. 995-1012 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/4511227\" target=\"_blank\" rel=\"noopener\">Wiley manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>M. Alioto, L. Giancane, G. Scotti, A. Trifiletti, \u201cLeakage Power Analysis Attacks: a Novel Class of Attacks to Nanometer Cryptographic Circuits,\u201d IEEE Trans. on Circuits and Systems \u2013 part I, vol. 57, no. 2, pp. 355-367, Feb. 2010 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/4806057\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>M. Alioto, G. Palumbo, M. Pennisi, \u201cUnderstanding the Effect of Process Variations on the Delay of Static and Domino Logic,\u201d IEEE Trans. on VLSI Systems, vol. 18, no. 5, pp. 697-710, May 2010 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/5169967\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>M. Alioto, M. Poli, S. Rocchi, \u201cA general power model of Differential Power Analysis attacks to static logic circuits,\u201d IEEE Trans. on VLSI Systems, vol. 18, no. 5, pp. 711-724, May 2010 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/5031897\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>A. Tajalli, M. Alioto, Y. Leblebici, \u201cImproving power-delay performance of ultralow-power subthreshold SCL circuits,\u201d IEEE Trans. on Circuits and Systems \u2013 part II, vol. 56, no. 2, pp. 127-131, Feb. 2009 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/4783079\/\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>M. Alioto, M. Poli, S. Rocchi, \u201cDifferential Power Analysis Attacks to Precharged Busses: a General Analysis for Symmetric-Key Cryptographic Algorithms,\u201d IEEE Trans. on Dependable and Secure Computing, vol. 7, no. 3, pp. 226-239, July-Sept. 2010 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/4752839\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>M. Agostinelli, M. Alioto, D. Esseni, L. Selmi, “Leakage-Delay Tradeoff in FinFET Logic Circuits: a Comparative Analysis with Bulk Technology,” IEEE Trans. on VLSI Systems, vol.18, no.2, pp. 232-245, Feb. 2010 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/4907217\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>M. Alioto, G. Palumbo, M. Poli, “Analysis and Modeling of Energy Consumption in RLC Tree Circuits,” IEEE Trans. on VLSI Systems, vol. 17, no. 2, pp. 278-291, Feb. 2009 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/4749363\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>M. Alioto, G. Palumbo, “Power-Aware Design of Nanometer MCML Tapered Buffers,” IEEE Trans. on Circuits and Systems \u2013 part II, vol. 55, no. 1, pp. 16-20, Jan. 2008 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/4384442\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>M. Alioto, G. Palumbo, “Very Fast Carry Energy Efficient Computation based on Mixed Dynamic\/Transmission-Gate Full Adders,” IEE Electronics letters, vol. 43, no. 13, pp. 707-709, 21st June 2007 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/4529717\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>\u00a0<\/p>\n<p><strong>International conferences (2006-today)<\/strong><\/p>\n<p><\/p>\n<p>A. Gupta, J. Vohra, M. Alioto, \u201cCogniVision: End-to-End SoC for Always-on Smart Vision with mW Power in 40nm,\u201d accepted to VLSI Symposium 2024, Honolulu (USA), June 2024<\/p>\n<p>A. Gupta, J. Vohra, V. Konandur, M. Alioto, \u201c122.7 TOPS\/W Stdcell-Based DNN Accelerator Based on Transition Density Data Representation, Clock-Less MAC Operation, Pseudo-Sparsity Exploitation in 40 nm,\u201d accepted to VLSI Symposium 2024, Honolulu (USA), June 2024<\/p>\n<p>A. K. Gundu, L. Fassio, M. Alioto, \u201cE-Textile Battery-Less Walking Step Counting System with <23 pW Power, Dual-Function Harvesting from Breathing, and No High-Voltage CMOS Process,\u201d accepted to VLSI Symposium 2024, Honolulu (USA), June 2024<\/p>\n<p>J. Vohra, A. Gupta, M. Alioto, \u201cImager with In-Sensor Event Detection and Morphological Transformations with 2.9 pJ\/pixel\u00d7frame Object Segmentation FOM for Always-On Surveillance in 40 nm,\u201d accepted to ISSCC 2024, San Francisco (USA), Feb. 2024 <span style=\"font-family: var( --e-global-typography-text-font-family ), Sans-serif; font-weight: var( --e-global-typography-text-font-weight );\">(IEEE manuscript, Scholar Bank draft)<\/span><\/p>\n<p>K. Ali Ahmed, R. Yang, P. Salamani, V. Rajanna, M. Alioto, \u201cSingle-Antenna Backscattered BLE5 Transmitter with up to 97m Range, 10.6 \u00b5W Peak Power for Purely-Harvested Green Systems,\u201d in Proc. of ESSCIRC 2023, Lisbon (Portugal), Sept. 2023 <span style=\"font-family: var( --e-global-typography-text-font-family ), Sans-serif; font-weight: var( --e-global-typography-text-font-weight );\">(IEEE manuscript, Scholar Bank draft)<\/span><\/p>\n<p>J. Vohra, K. Ali Ahmed, M. Alioto, \u201cA 0.4-V 12-bit Self-Calibrated SAR ADC with Offset Injection Assist Achieving 0.43 fJ\/conv-step,\u201c in Proc. of ESSCIRC 2023, Lisbon (Portugal), Sept. 2023 <span style=\"font-family: var( --e-global-typography-text-font-family ), Sans-serif; font-weight: var( --e-global-typography-text-font-weight );\">(IEEE manuscript, Scholar Bank draft)<\/span><\/p>\n<p>A. Gupta, S. Kumar, V. Konandur, S. Taneja, M. Alioto, \u201cVisual Content-Agnostic Novelty Detection Engine with 2.4 pJ\/pixel Energy and Two-Order of Magnitude DNN Activity Reduction in 40 nm,\u201d in Proc. of VLSI Symposium 2023, Kyoto (Japan), June 2023 <span style=\"font-family: var( --e-global-typography-text-font-family ), Sans-serif; font-weight: var( --e-global-typography-text-font-weight );\">(IEEE manuscript, Scholar Bank draft)<\/span><\/p>\n<p>J. Basu, L. Fassio, K. Ali, M. Alioto, \u201cSuper-Cutoff Analog Building Blocks for pW\/Stage Operation and Demonstration of 78-pW Battery-Less Light-Harvested Wake-Up Receiver down to Moonlight,\u201d in Proc. of VLSI Symposium 2023, Kyoto (Japan), June 2023 <span style=\"font-family: var( --e-global-typography-text-font-family ), Sans-serif; font-weight: var( --e-global-typography-text-font-weight );\">(IEEE manuscript, Scholar Bank draft)<\/span><\/p>\n<p>L. Fassio, O. Aiello, M. Alioto, \u201c38.4-pW, 0.14-mm2 Body-Driven Temperature-to-Digital Converter and Voltage Reference with 0.6-1.6-V Unregulated Supply for Battery-Less Systems,\u201d in Proc. of VLSI Symposium 2023, Kyoto (Japan), June 2023 <span style=\"font-family: var( --e-global-typography-text-font-family ), Sans-serif; font-weight: var( --e-global-typography-text-font-weight );\">(IEEE manuscript, Scholar Bank draft)<\/span><\/p>\n<p>Q. Fang, L. Lin, H. Zhang, T. Wang, M. Alioto, \u201cVoltage Scaling-Agnostic Counteraction of Side-Channel Neural Net Reverse Engineering via Machine Learning Compensation and Multi-Level Shuffling,\u201d in Proc. of VLSI Symposium 2023, Kyoto (Japan), June 2023 <span style=\"font-family: var( --e-global-typography-text-font-family ), Sans-serif; font-weight: var( --e-global-typography-text-font-weight );\">(IEEE manuscript, Scholar Bank draft)<\/span><\/p>\n<p>H. Zhang, L. Lin, Q. Fang, U. S. H. Kalingage, M. Alioto, \u201cSelf-Referenced Design-Agnostic Laser Voltage Probing Attack Detection with 100% Protection Coverage, 58% Area Overhead for Automated Design,\u201d in Proc. of VLSI Symposium 2023, Kyoto (Japan), June 2023 <span style=\"font-family: var( --e-global-typography-text-font-family ), Sans-serif; font-weight: var( --e-global-typography-text-font-weight );\">(IEEE manuscript, Scholar Bank draft)<\/span><\/p>\n<p>J. Basu, Sachin Taneja, V. Konandur Rajanna, T. Wang, M. Alioto, \u201cECC-Less Multi-Level SRAM Physically Unclonable Function and 127% PUF-to-Memory Capacity Ratio with No Bitcell Modification in 28nm,\u201d in Proc. of VLSI Symposium 2023, Kyoto (Japan), June 2023 <span style=\"font-family: var( --e-global-typography-text-font-family ), Sans-serif; font-weight: var( --e-global-typography-text-font-weight );\">(IEEE manuscript, Scholar Bank draft)<\/span><\/p>\n<p>U. De Alwis, X. Zhongheng, M. Alioto, \u201cTemporal Similarity-Based Computation Reduction for Video Transformers in Edge Camera Nodes,\u201d accepted to IEEE AICAS 2023 <span style=\"font-family: var( --e-global-typography-text-font-family ), Sans-serif; font-weight: var( --e-global-typography-text-font-weight );\">(IEEE manuscript, Scholar Bank draft)<\/span><\/p>\n<p>K. A. Ahmed, H. Okuhara, M. Alioto, \u201c55-pW\/pixel Peak Power Imager with Near-Sensor Novelty\/Edge Detection and DC-DC Converter-Less MPPT for Purely-Harvested Sensor Nodes,\u201d accepted to IEEE ISSCC 2023 <span style=\"font-family: var( --e-global-typography-text-font-family ), Sans-serif; font-weight: var( --e-global-typography-text-font-weight );\">(IEEE manuscript,<a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/237223\"> Scholar Bank draft<\/a>)<\/span><\/p>\n<p>U. De Alwis, M. Alioto, \u201cArchitecture for 3D Convolutional Neural Networks Based on Temporal Similarity Removal,\u201d accepted to IEEE ICECS 2022 <span style=\"font-family: var( --e-global-typography-text-font-family ), Sans-serif; font-weight: var( --e-global-typography-text-font-weight );\">(<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9970939\/\">IEEE manuscript<\/a>, <a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/237227\">Scholar Bank draft<\/a>)<\/span><\/p>\n<p>M. Alioto, \u201cFrom Less Batteries to Battery-Less: Enabling A Greener World through Ultra-Wide Power-Performance Adaptation down to pWs,\u201d in Proc. of IEEE ESSCIRC 2022 (invited), Milan (Italy), pp. 33-40, Sept. 2022 <span style=\"font-family: var( --e-global-typography-text-font-family ), Sans-serif; font-weight: var( --e-global-typography-text-font-weight );\">(IEEE manuscript, Scholar Bank draft)<\/span><\/p>\n<p><span style=\"font-family: var( --e-global-typography-text-font-family ), Sans-serif; font-weight: var( --e-global-typography-text-font-weight );\">O. Aiello, M. Alioto, \u201cCapacitance-Based Voltage Regulation- and Reference-Free Temperature-to-Digital Converter down to 0.3 V and 2.5 nW for Direct Harvesting,\u201d accepted to IEEE ESSCIRC 2022 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9911378\">IEEE manuscript<\/a>, Scholar Bank draft)<\/span><\/p>\n<p>H. Zhang, L. Lin, Q. Fang, M. Alioto, \u201cOn-Chip Laser Voltage Probing Attack Detection with 100% Area Coverage at Above\/Below the Bandgap Wavelength and Fully-Automated Design,\u201d accepted to IEEE VLSI Symposium 2022 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9830144\">IEEE manuscript<\/a>, <a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/231063\">Scholar Bank draft<\/a>)<\/p>\n<p>K. Ahmed, L. Lin, P. Salamani, M. Alioto, \u201cImager with Dynamic LSB Adaptation and Ratiometric Readout for Low-Bit Depth 5-\u00b5W Peak Power in Purely-Harvested Systems,\u201d accepted to IEEE VLSI Symposium 2022 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9830147\">IEEE manuscript<\/a>, <a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/237222\">Scholar Bank draft<\/a>)<\/p>\n<p>V. Konandur, H. Raghav, T. Wang, M. Alioto, \u201cFully-Digital Broadband Calibration-Less Impedance Monitor for Probe Insertion Detection against Power Analysis Attacks,\u201d accepted to IEEE VLSI Symposium 2022 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9830158\">IEEE manuscript<\/a>, <a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/231088\">Scholar Bank draft<\/a>)<\/p>\n<p>A. Gupta, V. Konandur, T. Salam, S. Jain, O. Aiello, P. Crovetti, M. Alioto, \u201cDDPMnet: All-Digital Pulse Density-Based DNN Architecture with 228 Gate Equivalents\/MAC Unit, 28-TOPS\/W and 1.5-TOPS\/mm2 in 40nm,\u201d accepted to IEEE CICC 2022 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9772786\">IEEE manuscript<\/a><span style=\"color: var( --e-global-color-text ); font-family: var( --e-global-typography-text-font-family ), Sans-serif; font-weight: var( --e-global-typography-text-font-weight );\">, <a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/237282\">Scholar Bank draft<\/a>)<\/span><\/p>\n<p>U. De Alwis, M. Alioto, \u201cTemporal Redundancy-Based Computation Reduction for 3D Convolutional Neural Networks,\u201d accepted to IEEE AICAS 2022 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9869903\">IEEE manuscript<\/a>, <a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/230886\">Scholar Bank draft<\/a>)<\/p>\n<p>Q. Fang, L. Lin, Y. Z. Wong, H. Zhang, M. Alioto, \u201cSide-Channel Attack Counteraction via Machine Learning Targeted Power Compensation for Post-Silicon HW Security Patching,\u201d accepted to IEEE ISSCC 2022 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9731755\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>, <a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/225716\">Scholar Bank draft<\/a>)<\/p>\n<p><\/p>\n<p>Q. Fang, M. Alioto, \u201cLast-round and Joint First\/Last-Round Power Analysis Attacks on PRESENT,\u201d accepted to IEEE AsianHOST 2021 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9699610\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>, <a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/225676\">Scholar Bank draft<\/a>)<\/p>\n<p><\/p>\n<p>S. Wu, K. De Silva, S. Gutgutia, B. Baas, M. Alioto, \u201cA 1448-Mpixel\/s, 84-pJ\/pixel Display Stream Compression Encoder in 28 nm for 4K Video Resolution,\u201d in Proc. of IEEE ASSCC 2021, Busan (Korea), Nov 2021 (<a href=\"https:\/\/ieeexplore.ieee.org\/abstract\/document\/9634771\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>, Scholar Bank draft)<\/p>\n<p><\/p>\n<p>L. Fassio, L. Lin, R. De Rose, M. Lanuzza, F. Crupi, M. Alioto, \u201cA 0.6-to-1.8V Trimming-Less CMOS Current Reference with Near-100% Power Utilization,\u201d accepted to IEEE ISICAS2021 (<a href=\"https:\/\/ieeexplore.ieee.org\/stamp\/stamp.jsp?arnumber=9916267\">IEEE manuscript<\/a>, <a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/191973\" target=\"_blank\" rel=\"noopener\">Scholar Bank draft<\/a>)<\/p>\n<p>P. Toledo, P. Crovetti, H. Klimach, S. Bampi, O. Aiello, M. Alioto, \u201cA 300mV-Supply, sub-nW Power Digital-Based Operational Transconductance Amplifier,\u201d accepted to IEEE ISICAS2021 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9442808\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>, Scholar Bank draft)<\/p>\n<p>V. Konandur Rajanna, S. Taneja, M. Alioto, \u201cA 109TOPS\/mm2 and 749-1,459TOPS\/W SRAM Buffer with In-Memory Inference and Prediction-Less Bitline Activity Reduction in 28nm,\u201d accepted to IEEE ESSCIRC 2021 ((IEEE manuscript, <a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/192142\" target=\"_blank\" rel=\"noopener\">Scholar Bank draft<\/a>)<\/p>\n<p>L. Fassio, L. Lin, R. De Rose, M. Lanuzza, F. Crupi, M. Alioto, \u201cTrimming-Less 0.2-V, 3.2-pW Voltage Reference Based on Corner-Aware Replica Combination with 1.6% Process Sensitivity, 1.4-mV Accuracy across PVT and Wafers,\u201d accepted to IEEE ESSCIRC 2021 (<a href=\"https:\/\/ieeexplore.ieee.org\/stamp\/stamp.jsp?arnumber=10007824\">IEEE manuscript<\/a>, <a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/237224\">Scholar Bank draft<\/a>)<\/p>\n<p>L. Lin, K. Ali Ahmed, P. S. Salamani, M. Alioto, \u201cBattery-Less IoT Sensor Node with PLL-Less WiFi Backscattering Communications in a 2.5-\u00b5W Peak Power Envelope,\u201d IEEE VLSI Symposium 2021, Kyoto (Japan), June 2021 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9492358\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>, <a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/192141\">Scholar Bank draft<\/a>)<\/p>\n<p>P. Agarwal, V. Konandur Rajanna, W. D. Toh, B. C. K. Tee, M. Alioto, \u201cFully-Digital Self-Calibrating Decoder with Sub-\u00b5W, 1.6fJ\/convstep and 0.0075mm2 per Receptor for Scaling to Human-Like Tactile Sensing Density,\u201d IEEE VLSI Symposium 2021, Kyoto (Japan), June 2021 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9492329\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>, <a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/192144\" target=\"_blank\" rel=\"noopener\">Scholar Bank draft<\/a>)<\/p>\n<p>U. De Alwis, M. Alioto, \u201cTempDiff: Temporal Difference-Based Feature Map-Level Sparsity Induction in CNNs with <4% Memory Overhead,\u201d accepted to IEEE AICAS 2021 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9458463\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>, <a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/189401\" target=\"_blank\" rel=\"noopener\">Scholar Bank draft<\/a>)<\/p>\n<p>S. Taneja, M. Alioto, \u201cUnified In-Memory Dynamic (TRNG) and Multi-Bit Static (PUF) Entropy Generation for Ubiquitous Hardware Security,\u201d in IEEE ISSCC Dig. Tech. Papers, Feb. 2021, pp. 498-499 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9366019\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>, <a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/191224\" target=\"_blank\" rel=\"noopener\">Scholar Bank draft<\/a>)<\/p>\n<p>T.-N. Pham, Q.-K. Trinh, I.-J. Chang, M. Alioto, \u201cSTT-BNN: A Novel Energy-efficient and Scalable BNN Accelerator Based on STT-MRAM,\u201d accepted to IEEE ISCAS 2021 (<a href=\"https:\/\/ieeexplore.ieee.org\/stamp\/stamp.jsp?arnumber=9605611\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>, Scholar Bank draft)<\/p>\n<p>O. Aiello, P. Crovetti, M. Alioto, \u201cCapacitance-to-Digital Converter for Operation under Uncertain Harvested Voltage down to 0.3V with No Trimming, Reference and Voltage Regulation,\u201d in IEEE ISSCC Dig. Tech. Papers, Feb. 2021, pp. 74-75 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9365846\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>, <a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/216938\" target=\"_blank\" rel=\"noopener\">Scholar Bank draft<\/a>)<\/p>\n<p>S. Taneja, M. Alioto, \u201cFully-Synthesizable All-Digital Unified Dynamic Entropy Generation, Extraction and Utilization in a Cryptographic Core for Constrained Secure Systems,\u201d in Proc. of IEEE ASSCC 2020, Nov. 2020 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9199880\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>, <a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/172972\" target=\"_blank\" rel=\"noopener\">Scholar Bank draft<\/a>)<\/p>\n<p>S. Jain, L. Lin, M. Alioto, \u201cBroad-Purpose In-Memory Computing for Signal Monitoring and Machine Learning Workloads Based on Commercial Bitcell,\u201d in Proc. of IEEE ASSCC 2020, Nov. 2020 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9199903\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>, <a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/172973\" target=\"_blank\" rel=\"noopener\">Scholar Bank draft<\/a>)<\/p>\n<p>J. H. Teo, K. Ali, M. Alioto, \u201cVoice Activity Detection with >83% Accuracy under SNR down to -3dB at 1.19\u00b5W and 0.07mm2 in 40nm,\u201d in Proc. of IEEE ASSCC 2020, Nov. 2020 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9336132\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>, <a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/172974\" target=\"_blank\" rel=\"noopener\">Scholar Bank draft<\/a>)<\/p>\n<p>L. Lin, S. Jain, M. Alioto, \u201cMulti-Sensor Platform with Five-Order-of-Magnitude System Power Adaptation down to 3.1nW and Sustained Operation under Moonlight Harvesting,\u201d in Proc. of VLSI Symposium 2020, Honolulu (USA), June 2020 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9162898\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>, Scholar Bank draft)<\/p>\n<p>Luigi Fassio, L. Lin, R. De Rose, M. Lanuzza, F. Crupi, M. Alioto, \u201cA 0.25-V, 5.3-pW Voltage Reference with 25-\u00b5V\/oC Temperature Coefficient, 140-\u00b5V\/V Line Sensitivity and 2,200-\u00b5m2 Area in 180nm,\u201d in Proc. of VLSI Symposium 2020, Honolulu (USA), June 2020 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9162872\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>, <a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/172976\" target=\"_blank\" rel=\"noopener\">Scholar Bank draft<\/a>)<\/p>\n<p>S. Taneja, M. Alioto, \u201cDeep Sub-pJ\/bit Low-Area Energy-Security Scalable SIMON Crypto-Core,\u201d in Proc. of ISCAS 2020, Seville (Spain), Oct 2020 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9180777\/\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>, <a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/191225\" target=\"_blank\" rel=\"noopener\">Scholar Bank draft<\/a>)<\/p>\n<p>S. Jain, L. Longyang, M. Alioto, \u201cLow-Overhead Drop-In Techniques to Extend the Energy-Performance Tradeoff in Microcontrollers Beyond VDD Scaling,\u201d in Proc. of ASSCC 2019, pp. 125-129, Macau (China), Nov. 2019 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9056919\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>, <a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/189801\" target=\"_blank\" rel=\"noopener\">Scholar Bank draft<\/a>)<\/p>\n<p>J. H. Teo, S. Cheng, M. Alioto, \u201cEnergy-Quality Scalable Analog-to-Digital Conversion and Machine Learning Engine in a 51.9 nJ\/frame Voice Activity Detector,\u201d in Proc. of ICECS 2019, pp. 174-177, Genoa (Italy), Nov. 2019 (<a href=\"https:\/\/ieeexplore.ieee.org\/abstract\/document\/8964767\/\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>, Scholar Bank draft)<\/p>\n<p>O. Aiello, P. Crovetti, A. Sharma, M. Alioto, \u201cFully-Synthesizable Current-Input ADCs for Ultra-Low Area and Minimal Design Effort,\u201d in Proc. of ICECS 2019, pp. 715-718, Genoa (Italy), Nov. 2019 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8964789\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>, <a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/189170\" target=\"_blank\" rel=\"noopener\">Scholar Bank draft<\/a>)<\/p>\n<p>M. Lanuzza, R. De Rose, F. Crupi, M. Alioto, \u201cAn Energy Aware Variation-Tolerant Writing Termination Control for STT-based Non Volatile Flip-Flops,\u201d in Proc. of ICECS 2019, pp. 158-161, Genoa (Italy), Nov. 2019 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8964742\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>, Scholar Bank draft)<\/p>\n<p>S. Taneja, M. Alioto, \u201cPhysically Unclonable Function Design Margin Reduction via In-Situ and PVT Sensor Fusion,\u201d in Proc. of ESSCIRC 2019, pp. 61-64, Krakow (Poland), Oct 2019 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8902733\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>, Scholar Bank draft)<\/p>\n<p>L. Lin, S. Jain, M. Alioto, \u201cIntegrated Power Management and Microcontroller for Ultra-Wide Power Adaptation down to nW,\u201d VLSI Symposium 2019, Kyoto (Japan), pp. C178-179, June 2019 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8778085\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>O. Aiello, P. Crovetti, M. Alioto, \u201cWake-Up Oscillators with pW Power Consumption in Dynamic Leakage Suppression Logic,\u201d in Proc. of IEEE ISCAS 2019, Sapporo (Japan), May 2019 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8702365\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>F. Frustaci, P. Corsonello, S. Perri, M. Alioto, \u201cEnergy-Quality Scalable Adders Based on Nonzeroing Bit Truncation,\u201d in Proc. of IEEE ISCAS 2019, Sapporo (Japan), May 2019 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8561219\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, S. Taneja, \u201cEnabling Ubiquitous Hardware Security via Energy-Efficient Primitives and Systems,\u201d in Proc. of IEEE CICC 2019 (invited), Austin (USA), April 2019 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8780123\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0<a href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/191222\" target=\"_blank\" rel=\"noopener\">Scholar Bank draft<\/a>)<\/p>\n<p>V. Konandur, M. Alioto, \u201cLow-Swing Links with Dynamic Energy-Quality Trade-off for Error-Resilient Applications,\u201d in Proc. of IEEE CICC 2019, Austin (USA), April 2019 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8780323\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>S. Wu, S. Gutgutia, M. Alioto, B. Baas, \u201cDisplay Stream Compression Encoder Architectures for Real-time 4K and 8K Video Encoding,\u201d accepted to Asilomar 2018 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8645369\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>O. Aiello, P. Crovetti, M. Alioto, \u201cA Sub\u2010Leakage pW\u2010Power Hz Range Relaxation Oscillator Operating with 0.3V\u20101.8V Unregulated Supply,\u201d\u00a02018 VLSI Symposium on VLSI Circuits Digest of Technical Papers, C11-4, Honolulu (USA), June 2018 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8502413\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>S. Wu, S. Gutgutia, M. Alioto, B. Baas, \u201cDisplay Stream Compression Encoder Architectures for Real-time 4K and 8K Video Encoding,\u201d accepted to Asilomar 2018 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8645369\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>L. Lin, S. Jain, M. Alioto, \u201cA 595pW 14pJ\/cycle Microcontroller with Dual-mode Standard Cells and Self-startup for Battery-Indifferent Distributed Sensing,\u201d in IEEE ISSCC Dig. Tech. Papers, Feb. 2018, pp. 44-45 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8310175\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>Q. K. Trinh, S. Ruocco, M. Alioto, \u201cNovel Time-Based Sensing Scheme for STT-MRAMs,\u201d in Proc. of ISCAS 2018, pp. 1151-1154, Florence (Italy), May 2018 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8350966\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>G. Santoro, M. R. Casu, V. Peluso, A. Calimera, M. Alioto, \u201cDesign-Space Exploration of Pareto-Optimal Architectures for Deep Learning with DVFS,\u201d in Proc. of ISCAS 2018, pp. 1151-1154, Florence (Italy), May 2018 (<a href=\"https:\/\/ieeexplore.ieee.org\/abstract\/document\/8351685\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>O. Aiello, P. Crovetti, M. Alioto, \u201cFully Synthesizable, Rail-to-Rail Dynamic Voltage Comparator for Operation down to 0.3V,\u201d in Proc. of ISCAS 2018, Florence (Italy), May 2018 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8351106\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>G. Santoro, M. R. Casu, V. Peluso, A. Calimera, M. Alioto, \u201cEnergy-performance design exploration of a low-power microprogrammed deep-learning accelerator,\u201d in Proc. of DATE 2018, pp. 1151-1154, Dresden (Germany), March 2018 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8342185\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>A. Alvarez, G. Ponnusamy, M. Alioto, \u201cEQSCALE: Energy-Quality Scalable Feature Extraction Engine for Sub-mW Real-time Video Processing with 0.55 mm2 Area in 40nm CMOS,\u201d in Proc. of ASSCC 2017, pp. 241-244 , Seoul (Korea), Nov. 2017 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8240261\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>S. Taneja, A. Alvarez, G. Sadagopan, M. Alioto, \u201cA Fully-Synthesizable C-Element Based PUF Featuring Temperature Variation Compensation with Native 2.8% BER, 1.02fJ\/b at 0.8-1.0V in 40nm,\u201d in Proc. of ASSCC 2017, pp. 301-304, Seoul (Korea), Nov. 2017 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8240276\/\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>L. Lin, S. Jain, M. Alioto, \u201cReconfigurable Clock Networks for Random Skew Mitigation from Sub-Threshold to Nominal Voltage,\u201d in IEEE ISSCC Dig. Tech. Papers, Feb. 2017, pp. 440-441 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/7870450\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, \u201cEnergy-Quality Scalable Adaptive VLSI Circuits and Systems beyond Approximate Computing,\u201d in Proc. of IEEE DATE 2017 (invited), Lausanne (Switzerland), pp. 127-132, March 2017 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/7926970\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>R. De Rose, M. Lanuzza, F. Crupi, G. Siracusano, R. Tomasello, G. Finocchio, M. Carpentieri, M. Alioto, \u201cA Variation-Aware Simulation Framework for Hybrid CMOS\/Spintronic Circuits,\u201d in Proc. of ISCAS 2017 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8050920\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, G. Scotti, A. Trifiletti, \u201cDesign-Oriented Models for Quick Estimation of Path Delay Variability via the Fan-Out-of-4 Metric,\u201d in print on Proc. of ISCAS 2017 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8050910\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>L. Lin, K. Trinh Quang, M. Alioto, \u201cTransistor Sizing Strategy for Simultaneous Energy-Delay Optimization in CMOS Buffers,\u201d in print on Proc. of ISCAS 2017 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8050997\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>D. Esposito, A. G. M. Strollo, M. Alioto, \u201cPower-Precision Scalable Latch Memories,\u201d in print on Proc. of ISCAS 2017 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8050995\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>S. Jain, M. Alioto, \u201cA Closed-form Energy Model for VLSI Circuits under Wide Voltage Scaling,\u201d in Proc. of ICECS 2016, pp. 548-551, Monaco, Dec. 2016 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/7841260\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>S. Timarchi, M. Alioto, \u201cUltra-Low Voltage Standard Cell Libraries: Design Strategies and a Case Study,\u201d in Proc. of ICECS 2016, pp. 520-523, Monaco, Dec. 2016 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/7841253\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>V. Peluso, A. Calimera, E. Macii, M. Alioto, \u201cUltra-Fine Grain Vdd-Hopping for Energy-Efficient Multi-Processor SoCs,\u201d in Proc. of VLSI-SoC 2016, pp. 1-6 , Tallinn (Estonia), Sept. 2016 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/7753580\/\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>Y. Zhang, M. Khayatzadeh, K. Yang, M. Saligane, M. Alioto, D. Blaauw, D. Sylvester, \u201ciRazor: 3-Transistor Current-Based Error Detection and Correction in an ARM Cortex-R4 Processor,\u201d in IEEE ISSCC Dig. Tech. Papers, Feb. 2016, pp. 160-161 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8060508\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>M. Khayatzadeh, M. Saligane, J. Wang, M. Alioto, D. Blaauw, D. Sylvester, \u201cA Reconfigurable Dual Port Memory with Error Detection and Correction in 28nm FDSOI,\u201d in IEEE ISSCC Dig. Tech. Papers, Feb. 2016, pp. 310-311 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/7418031\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>K. T. Quang, S. Ruocco, M. Alioto, \u201cBoosted Sensing for Enhanced Read Stability in STTMRAMs,\u201d ISCAS 2016, pp. Montreal (Canada), May 2016 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/7527471\/\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>K. T. Quang, S. Ruocco, M. Alioto, \u201cSTT-MRAM Write Energy Minimization via Area Optimization Under Dynamic Voltage Scaling,\u201d ISCAS 2016, Montreal (Canada), May 2016 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/7539172\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>M. Khayatzadeh, F. Frustaci, D. Blaauw, D. Sylvester, M. Alioto, \u201cA Reconfigurable Sense Amplifier with 3X Offset Reduction in 28nm FDSOI CMOS,\u201d in Proc. of IEEE Symposium on VLSI Circuits, 2015, pp. 5\u20139 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/7231284\/\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, E. Consoli, G. Palumbo, \u201cComparative Analysis of the Robustness of Master-Slave Flip-Flops Against Variations,\u201d accepted to ICECS 2015, Cairo (Egypt), Dec. 2015 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/7440263\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>F. Frustaci, D. Blaauw, D. Sylvester, M. Alioto, \u201cBetter-than-Voltage Scaling Energy Reduction in Approximate SRAMs via Bit Dropping and Bit Reuse,\u201d in Proc. of PATMOS 2015, Salvador (Brazil), Sept 2015 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/7347598\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>Massimo Alioto, Gaetano Palumbo, Elio Consoli, \u201cPVT Variations in Differential Flip-Flops: A Comparative Analysis,\u201d in Proc. of ECCTD 2015, Trondheim (Norway) (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/7300081\/\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>Massimo Alioto, Gaetano Palumbo, Elio Consoli, \u201cVariability Budget in Pulsed Flip-Flops,\u201d in Proc. of NEWCAS 2015, Grenoble (France), June 2015 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>W. Zhao, Y. Ha, M. Alioto, \u201cAES Architectures for Minimum-Energy Operation and Silicon Demonstration in 65nm with Lowest Energy per Encryption,\u201d in Proc. of ISCAS 2015, pp. 2349-2352, Lisbon (Portugal), May 2015 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/7169155\/\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>M. Shoaran, A. Tajalli, M. Alioto, Y. Leblebici, \u201cJitter Analysis and Measurement in Subthreshold Source-Coupled Differential Ring Oscillators,\u201d in Proc. of ISCAS 2015, pp. 157-160, Lisbon (Portugal), May 2015 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/7168594\/\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>K. Trinh Quang, S. Ruocco, M. Alioto, \u201cModeling the Impact of Dynamic Voltage Scaling on 1T-1J STT-RAM Write Energy and Performance,\u201d in Proc. of ISCAS 2015, pp. 2313-2316, Lisbon (Portugal), May 2015 (<a href=\"https:\/\/ieeexplore.ieee.org\/abstract\/document\/7169146\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>A. Alvarez, W. Zhao, M. Alioto, \u201c15-fJ\/bit Static Physically Unclonable Functions for Secure Chip Identification with <2% Native Bit Instability and 140X Intra\/Inter PUF Hamming Distance Separation in 65nm,\u201d in IEEE ISSCC Dig. Tech. Papers, Feb. 2015, pp. 258-259. (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, D. Esseni, \u201cComparative Evaluation of Tunnel-FET Ultra-Low Voltage SRAM Bitcell and Impact of Variations,\u201d in Proc. of VARI 2014, Palma de Mallorca (Spain), Sept. 2014 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/6957083\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, E. Consoli, G. Palumbo, \u201cAnalysis and Comparison of Variations in Double Edge Triggered Flip-Flops,\u201d in Proc. of VARI 2014, Palma de Mallorca (Spain), Sept. 2014 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/6957076\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, D. Esseni, \u201cPerformance and Impact of Process Variations in Tunnel-FET Ultra-Low Voltage Digital Circuits,\u201d in proc. of ACM SBCCI 2014, Aracaju (Brazil), Sept. 2014 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/6994652\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>L. Artola, G. Hubert, M. Alioto, \u201cComparative SET Evaluation of Layout cells in FinFET Technology,\u201d in print on proc. of ESREF 2014 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>D. Esseni, M. Alioto, \u201cDevice-Circuit Co-Design and Comparison of Ultra-Low Voltage Tunnel-FET and CMOS Digital Circuits,\u201d in proc. of NEWCAS 2014, pp. 321-324, Trois-Riviere (Canada), June 2014 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/6934047\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, S. Bongiovanni, G. Scotti, A. Trifiletti, \u201cLeakage Power Analysis Attacks Against a Bit Slice Implementation of the Serpent Block Cipher,\u201d in print on proc. of MIXDES 2014 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/6872193?arnumber=6872193\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>F. Frustaci, M. Khayatzadeh, D. Blaauw, D. Sylvester, M. Alioto, \u201cA 32kb SRAM for Error-Free and Error-Tolerant Applications with Dynamic Energy-Quality Management in 28nm CMOS,\u201d in IEEE ISSCC Dig. Tech. Papers, Feb. 2014, pp. 244-245 <a href=\"https:\/\/ieeexplore.ieee.org\/document\/7063974\" target=\"_blank\" rel=\"noopener\">(IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<br \/>.<br \/>L. Freyman, D. Fick, D. Blaauw, D. Sylvester, M. Alioto, \u201cA 346um2 Reference-Free Sensor Interface for Highly Constrained Microsystems in 28nm CMOS,\u201d in print on proc. of ASSCC 2013, Singapore, Nov. 2013. (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>Y.-P. Chen, Y. Lee, J.-Y. Sim, M. Alioto, D. Blaauw, D. Sylvester, \u201c45pW ESD Clamp Circuit for Ultra-Low Power Applications,\u201d in print on proc. of CICC 2013, San Jose (USA), Sept. 2013. (<a href=\"https:\/\/ieeexplore.ieee.org\/abstract\/document\/6658522\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>M. Tache, V. Beiu, W. Ibrahim, F. Kharbash, M. Alioto, \u201cSizing for Static Noise Margins Revisited,\u201d in Proc. of VARI 2013, Karlsruhe (Germany), Sept. 2013. (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/6523623\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>V. Beiu, \u00a0A. Beg, \u00a0W. Ibrahim, \u00a0F. Kharbash, \u00a0M. Alioto, \u201cEnabling Sizing for Enhancing the Static Noise Margins,\u201d in print on Proc. of ISQED 2013, Santa Clara (California), March 2013. (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/6523623\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>S. Bang, D. Blaauw, D. Sylvester, M. Alioto, \u201cReconfigurable Sleep Transistor for GIDL Reduction in Ultra-Low Standby Power Systems,\u201d in Proc. of CICC 2012, San Jose, California, Sept. 2012. (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/6330628\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, E. Consoli, J. Rabaey, \u201cEChO Power Management Unit with Reconfigurable Switched-Capacitor Converter in 65 nm CMOS,\u201d in Proc. of CICC 2012, San Jose, California, Sept. 2012. (<a href=\"https:\/\/ieeexplore.ieee.org\/abstract\/document\/6330629\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>J. Richmond, M. John, L. Alarcon, W. Zhou, W. Li, T.-T. Liu, M. Alioto, S. R. Sanders, J. M. Rabaey, \u201cActive RFID: A Perpetual Wireless Communications Platform for Sensors,\u201d in print on Proc. of ESSCIRC 2012, Bordeaux (France), Sept. 2012. (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/6341348\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, G. Palumbo, M. Pennisi, \u201cA Simple Keeper Topology to Reduce Delay Variations in Nanometer Domino Logic,\u201d in Proc. of ISCAS 2012, pp. 1576-1579, Seoul (Korea), May 2012. (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/6271554\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>F. Crupi, P. Magnone, M. Alioto, J. Franco, G. Groeseneken, \u201cEarly Assessment of Emerging Technologies for VLSI Logic Circuits from Experimental Measurements,\u201d in Proc. of ICSICT 2012 (invited). (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>E. Consoli, M. Alioto, G. Palumbo, J. Rabaey, \u201cConditional Push-Pull Pulsed Latch with 726 fJ\u2022ps Energy Delay Product in 65nm CMOS,\u201d in Proc. of ISSCC 2012, San Francisco (USA), Feb. 2012. (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, \u201c’Impact of NMOS\/PMOS Imbalance in Ultra-Low Voltage CMOS Standard Cells,\u201d in Proc. of ECCTD 2011, pp. 557-561, Linkoping (Sweden), Aug. 2011. (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/6043407\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>F. Frustaci, P. Corsonello, M. Alioto, \u201cOptimization and Evaluation of Tapered-VTH Approach for Energy-Efficient CMOS Buffers,\u201d in print on Proc. of ECCTD 2011, Aug. 2011. (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/6043603\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>F. Crupi, M. Alioto, J. Franco, P. Magnone, B. Kaczer, G. Groeseneken, J. Mitard, L. Witters, T. Y. Hoffmann, \u201cExperimental Analysis of Buried SiGe pMOSFETs from the Perspective of Aggressive Voltage Scaling,\u201d in print on Proc. of ISCAS 2011, Rio de Janeiro (Brazil), May 2011. (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/5938049\/\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>D. Baccarin, D. Esseni, M. Alioto, \u201cA Novel Back-Biasing Low-Leakage Technique for FinFET Forced Stacks,\u201d in print on Proc. of ISCAS 2011, Rio de Janeiro (Brazil), May 2011. (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/5938007\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, E. Consoli, G. Palumbo, \u201cDET FF Topologies: A Detailed Investigation in the Energy-Delay-Area Domain,\u201d in print on Proc. of ISCAS 2011, Rio de Janeiro (Brazil), May 2011. (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/5937627\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>F. Frustaci, P. Corsonello, M. Alioto, \u201cTapered-VTH CMOS Buffer Design for Improved Energy Efficiency in Deep Nanometer Technology,\u201d in print on Proc. of ISCAS 2011, Rio de Janeiro (Brazil), May 2011. (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/5938006\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>M. Djukanovic, L. Giancane, G. Scotti, A. Trifiletti, M. Alioto, \u201cLeakage Power Analysis Attacks: Effectiveness on DPA Resistant Logic Styles under Process Variations,\u201d in print on Proc. of ISCAS 2011, Rio de Janeiro (Brazil), May 2011. (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/5937998\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, \u201cLow-Standby Current 4T FinFET Buffers: Analysis and Evaluation below 45 nm,\u201d in print on Proc. of ICM 2010, Cairo (Egypt), Dec. 2010. (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/5696143\/\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, E. Consoli, G. Palumbo, \u201cNanometer Flip-Flops Design in the E-D Space,\u201d in print on Proc. of ICM 2010, Cairo (Egypt), Dec. 2010. (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/5696091\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, E. Consoli, G. Palumbo, \u201cPhysical Design Aware Selection of Energy-Efficient and Low-Energy Nanometer Flip-Flops,\u201d in print on Proc. of ICM 2010, Cairo (Egypt), Dec. 2010. (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/5696206\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>J. Mitard, L. Witters, M. Garcia Bardon, P. Christie, J. Franco, A. Mercha, P. Magnone, M. Alioto, F. Crupi, L.-A. Ragnarsson, A. Hikavyy, B. Vincent, T. Chiarella, R. Loo, J. Tseng, S. Yamaguchi, S. Takeoka, W.-W. Wang, P. Absil, T. Hoffmann, \u201cSub-nm EOT high-mobility SiGe-55% channel pFETs: Delivering high performance at scaled VDD,\u201d accepted to IEEE IEDM 2010, San Francisco (USA), Dec. 2010. (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>K. Agawa, M. Alioto, W. Zhou, T.-T. Liu, L. Alarcon, K. Hajkazemshirazi, M. John, J. Richmond, W. Li, J. Rabaey, \u201cDesign and Verification of an Ultra-Low-Power Active RFID Tag with Multiple Power Domains,\u201d in Proc. of SASIMI2010, Taipei (Taiwan), Oct. 2010. (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, E. Consoli, G. Palumbo, \u201cPhysical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI Circuits,\u201d in print on Proc. of PATMOS 2010, Grenoble (France), Sept. 2010. (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, \u201cA Scalable Low-Entropy Detector to Counteract the Parameter Variability effects in TRBGs,\u201d in print on Proc. IMTC 2010, Austin (USA), May 2010. (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/5488044\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>M. Merrett, Y. Wang, M. Alioto, M. Zwolinski, \u201cDesign Metrics for RTL Level Estimation of Delay Variability Due to Intradie (Random) Variations,\u201d in Proc. of ISCAS 2010, pp. 2498-2501, Paris (France), May 2010 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/5537133\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>P. Magnone, F. Crupi, M. Alioto, B. Kaczer, \u201cExperimental Study of Leakage-Delay Trade-off in Germanium pMOSFETs for Logic Circuits,\u201d in Proc. of ISCAS 2010, pp. 1699-1702, Paris (France), May 2010 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/5537514\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, \u201cAnalysis of Layout Density in FinFET Standard Cells and Impact of Fin Technology,\u201d in Proc. of ISCAS 2010, pp. 3204-3207, Paris (France), May 2010. (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/5537930\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, P. Bennati, R. Giorgi, \u201cExploiting Locality to Improve Leakage Reduction in Embedded Drowsy I-Caches at Same Area\/Speed,\u201d in Proc. of ISCAS 2010, pp. 37-40, Paris (France), May 2010 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/5537105\/\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, \u201cClosed-Form Analysis of DC Noise Immunity in Subthreshold CMOS Logic Circuits,\u201d in Proc. of ISCAS 2010, pp. 1468-1471, Paris (France), May 2010\u00a0 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/5537340\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, E. Consoli, G. Palumbo, \u201cClock Distribution in Clock Domains with Dual-Edge-Triggered Flip-Flops to improve Energy-Efficiency,\u201d in Proc. of ISCAS 2010, pp. 321-324, Paris (France), May 2010 (<a href=\"https:\/\/ieeexplore.ieee.org\/document\/5537828\/\" target=\"_blank\" rel=\"noopener\">IEEE manuscript<\/a>,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, E. Consoli, G. Palumbo, \u201cOptimum Clock Slope for Flip-Flops within a Clock Domain: Analysis and a Case Study,\u201d in Proc. of ICECS 2009, pp. 275-278, Hammamet (Tunisia), Dec. 2009 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, G. Palumbo, M. Pennisi, \u201cAnalysis of the Impact of Random Process Variations in CMOS Tapered Buffers,\u201d in Proc. of ICECS 2009, pp. 57-60, Hammamet (Tunisia), Dec. 2009 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, L. Giancane, G. Scotti, A. Trifiletti, \u201cLeakage Power Analysis Attacks: Theoretical Analysis and Impact of Variations,\u201d in Proc. of ICECS 2009, pp. 85-88, Hammamet (Tunisia), Dec. 2009 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, E. Consoli, G. Palumbo, \u201cDependence of Differential Flip-Flops Performance on Clock Slope and Relaxation of Clock Network Design,\u201d in Proc. of ICM 2009, pp. 110-113, Marrakech (Morocco), Dec. 2009 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, M. Poli, S. Rocchi, \u201cLow-Overhead Countermeasures to protect Pre-charged Busses against Power Analysis Attacks,\u201d in Proc. of ICM 2009, pp. 159-162, Marrakech (Morocco), Dec. 2009 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, L. Giancane, G. Scotti, A. Trifiletti, \u201cLeakage Power Analysis Attacks: Well-Defined Procedure and First Experimental Results,\u201d in Proc. of ICM 2009, pp. 46-49, Marrakech (Morocco), Dec. 2009 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, \u201cAnalysis and Evaluation of Layout Density of FinFET Logic Gates,\u201d in Proc. of ICM 2009, pp. 106-109, \u00a0Marrakech (Morocco), Dec. 2009 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, E. Consoli, G. Palumbo, \u201cImpact of Clock Slope on Energy\/Delay of Pulsed Flip-Flops and Optimum Clock Domain Design,\u201d in Proc. of ECCTD 2009, pp. 61-64, Antalya (Turkey), Aug. 2009 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, E. Consoli, G. Palumbo, M. Pennisi, \u201cCorrect Procedures to Evaluate the Effect of Intradie Variations on the Delay Variability of Digital Circuits,\u201d in Proc. of ECCTD 2009, pp. 779-782, Antalya (Turkey), Aug. 2009 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, E. Consoli, G. Palumbo, \u201cMetrics and Design Considerations on the Energy-Delay Tradeoff of Digital Circuits,\u201d in Proc. of ISCAS 2009, pp. 3150-3153, Taipei (Taiwan), May 2009 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, Y. Leblebici, \u201cAnalysis and Design of Ultra-Low Power Subthreshold MCML Gates,\u201d in Proc. of ISCAS 2009, pp. 2557-2560, Taipei (Taiwan), May 2009 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, \u201cUnderstanding Loading Effects of RC Uniform Interconnects,\u201d in Proc. of ISCAS 2009, pp. 2269-2272, Taipei (Taiwan), May 2009 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, S. Badel, Y. Leblebici, \u201cOptimization of Wire Grid Size for Differential Routing and Impact on the Power-Delay-Area Tradeoff,\u201d in Proc. of ISCAS 2009, pp. 1285-1288, Taipei (Taiwan), May 2009 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, \u201cCAD Models of the Input Admittance of RC Wires: Comparison and Selection Strategies,\u201d in Proc. of ICM 2008, pp. 154-157, Sharjah (United Arab Emirates), Dec. 2008 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, M. Poli, G. Palumbo, \u201cCompact and Simple Output Transition Time Model in Nanometer CMOS Gates,\u201d in Proc. of ICM 2008, pp. 235-238, Sharjah (United Arab Emirates), Dec. 2008 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, M. Poli, S. Rocchi, \u201cPower Analysis Attacks to Cryptographic Circuits: a Comparative Analysis of DPA and CPA,\u201d in Proc. of ICM 2008, pp. 308-311, Sharjah (United Arab Emirates), Dec. 2008 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, Y. Leblebici, \u201cCircuit techniques to reduce the supply voltage limit of subthreshold MCML circuits,\u201d in Proc. of VLSI-SoC 2008, pp. 239-244, Rhodes Island (Greece), Oct. 2008 (INVITED) (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>Armin Tajalli, Massimo Alioto, Elizabeth J. Brauer, Yusuf Leblebici, \u201cDesign of High Performance Subthreshold Source-Coupled Logic Circuits,\u201d in Proc. of PATMOS 2008, pp. 21-30, Lisbon (Portugal), Sep. 2008 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>Matteo Agostinelli, Massimo Alioto, David Esseni, Luca Selmi, \u201cDesign and evaluation of mixed 3T-4T FinFET stacks for leakage reduction,\u201d in Proc. of PATMOS 2008, pp. 31-41, Lisbon (Portugal), Sep. 2008 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, G. Palumbo, M. Pennisi, \u201cUnderstanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic,\u201d in Proc. of PATMOS 2008, pp. 136-145, Lisbon (Portugal), Sep. 2008 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, G. Palumbo, M. Pennisi, \u201cAnalysis of the impact of process variations on static logic circuits versus fan-in,\u201d in Proc. of ICECS 2008, pp. 137-140, Malta, Aug. 2008 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, G. Palumbo, M. Poli, \u201cEnergy Evaluation in RLC Tree Circuits with Exponential Input,\u201d in Proc. of ICECS 2008, pp. 578-581, Malta, Aug. 2008 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, L. Fondelli, S. Rocchi, “Analysis and Performance Evaluation of Area-Efficient True Random Bit Generators on FPGAs”, in Proc. of ISCAS 2008, pp. 1572-1575, Seattle (USA), May 2008 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>A. Tajalli, F. K. Gurkaynak, Y. Leblebici. M. Alioto, E. J. Brauer, “Improving the Power-Delay Product in SCL Circuits Using Source Follower Output Stage”, in Proc. of ISCAS 2008, pp. 145-148, Seattle (USA), May 2008 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, G. Palumbo, M. Poli, “Explicit Energy Evaluation in RLC Tree Circuits with Ramp Inputs”, in Proc. of ISCAS 2008, pp. 2865-2868, Seattle (USA), May 2008 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, G. Palumbo, “Power-Delay Optimization in MCML Tapered Buffers”, in Proc. of ISCAS 2008, pp. 141-144, Seattle (USA), May 2008 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, M. Poli, S. Rocchi, “A General Model for Differential Power Analysis Attacks to Static Logic Circuits”, in Proc. of ISCAS 2008, pp. 3346-3349, Seattle (USA), May 2008 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, G. Palumbo, M. Poli, “Efficient and Accurate Models of Output Transition Time in CMOS Logic”, Proc. of ICECS 2007, pp. 1264-1267, Marrakech (Morocco), Dec. 2007 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p><\/p>\n<p>M. Alioto, “A Simple and Accurate Model of Input capacitance for Power Estimation in CMOS logic”, Proc. of ICECS 2007, pp. 431-434, Marrakech (Morocco), Dec. 2007 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, G. Palumbo, M. Poli, “Energy Consumption in RLC Tree Circuits”, Proc. of ECCTD 2007, pp. 771-774, Sevilla (Spain), Aug. 2007 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, G. Palumbo, “Very High-Speed Carry Computation based on Mixed Dynamic\/Transmission-Gate Full Adders”, Proc. of ECCTD 2007, pp. 799-802, Sevilla (Spain), Aug. 2007 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, M. Poli, S. Rocchi, V. Vignoli, “A General Model of DPA Attacks to Precharged Busses in Symmetric-Key Cryptographic Algorithms”, Proc. of ECCTD 2007, pp. 368-371, Sevilla (Spain), Aug. 2007 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Agostinelli, M. Alioto, D. Esseni, L. Selmi, “Trading off static power and dynamic performance in CMOS digital circuits: bulk versus double gate SOI MOSFETs”, Proc. of ESSDERC 2007, pp. 191-194, Munich (Germany), Sept. 2007 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, G. Palumbo, “Delay Variability Due to Supply Variations in Transmission-Gate Full Adders”, Proc. of ISCAS 2007, pp. 3732-3735, New Orleans (USA), May 2007 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, “Maximum-Period PRBGs Derived From A Piecewise Linear One-Dimensional Map”, Proc. of ISCAS 2007, pp. 693-696, New Orleans (USA), May 2007 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, G. Palumbo, “High-Speed\/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology”, Proc. of ISCAS 2007, pp. 2998-3001, New Orleans (USA), May 2007 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, G. Palumbo, “Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects”, Proc. of SCAS 2007, pp. 3255-3258, New Orleans (USA), May 2007 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, M. Poli, S. Rocchi, V. Vignoli, “Mixed Techniques to Protect Precharged Busses against Differential Power Analisys Attacks”, Proc. of ISCAS 2007, pp. 861-864, New Orleans (USA), May 2007 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>T. Addabbo, M. Alioto, A. Fort, M. Mugnaini, S. Rocchi, V. Vignoli, “Implementation-Efficient Maximum-Period Nonlinear Congruential Generators”, Proc. of IMTC 2007, Warsaw (Poland), May. 2007 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, “Efficient Post-Processing Module for a Chaos-based Random Bit Generator”, Proc. of ICECS2006, pp. 1224-1227, Nice (France), Dec. 2006 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, G. Palumbo, “Modeling of Delay Variability due to Supply Variations in Pass-Transistor and Static Full Adders”, Proc. of ICECS2006, pp. 518-521, Nice (France), Dec. 2006 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, R. Mita, G. Palumbo, “A Design Methodology for High-Speed Low-Power MCML Frequency Dividers”, Proc. of ICECS2006, pp. 1308-1311, Nice (France), Dec. 2006 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, “Entropy Enhancement in a Chaos-Based True Random Bit Generators”, Proc. of NOLTA 2006, pp. 372-378, Bologna (Italy), Sept. 2006 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, M. Poli, S. Rocchi, V. Vignoli, “Techniques to Enhance the Resistance of Precharged Busses to Differential Power Analysis”, Proc. of PATMOS 2006, pp. 624-633, Montpellier (France), Sept. 2006 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, M. Poli, S. Rocchi, V. Vignoli, “Power Modeling of Precharged Address Bus and Application to Multi-bit DPA Attacks to DES Algorithm”, Proc. of PATMOS 2006, pp. 593-602, Montpellier (France), Sept. 2006 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, A. D. Grasso, G. Palumbo, “Design of Cascaded ECL Gates with a Power Constraint”, Proc. of PRIME 2006, pp. 233-236, Otranto (Italy), June 2006 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, “A Technique to Design High Entropy Chaos-Based True Random Bit Generators”, Proc. of ISCAS 2006, pp. 1183-1186, Kos (Greece), May 2006 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, G. Palumbo, M. Poli, “Efficient Output Transition Time Modeling in CMOS Gates with Ramp\/Exponential Inputs”, Proc. of ISCAS 2006, pp. 5127-5130, Kos (Greece), May 2006 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, L. Pancioni, S. Rocchi, V. Vignoli, “Analysis and Design of MCML Gates with Hysteresis”, Proc. of ISCAS 2006, pp. 1263-1266, Kos (Greece), May 2006 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, G. Palumbo, “Nanometer MCML Gates: Models and Design Considerations”, Proc. of ISCAS 2006, pp. 3862-3865, Kos (Greece), May 2006 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>M. Alioto, G. Palumbo, “Delay Uncertainty Due to Supply Variations in Static and Dynamic Full Adders”, Proc. of ISCAS 2006, pp. 767-770, Kos (Greece), May 2006 (IEEE manuscript,\u00a0Scholar Bank draft)<\/p>\n<p>T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, “Uniform-Distributed Noise Generator Based on a Chaotic Circuit”, Proc of IMTC 2006, pp. 1156-1160, Sorrento (Italy), April 2006 (IEEE manuscript,\u00a0Scholar Bank draft)<a style=\"font-weight: var( --e-global-typography-text-font-weight ); background-color: #f5f5f5; color: #003d7c; font-family: 'Helvetica Neue Lt', Helvetica, Arial, sans-serif; font-size: 13px; letter-spacing: 0.52px;\" href=\"https:\/\/scholarbank.nus.edu.sg\/handle\/10635\/191220\">Trends in Hardware Security: from Basics to ASICs<\/a><\/p>\n<p><\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"<p>Editorials M. Alioto, \u201cOpening of the 2023 Editorial Year \u2013 This Coda as Prelude of Next TVLSI Cycle with Sustained Growth,\u201d IEEE Trans. on VLSI Systems, vol. 31, no. 1, pp. 1-2, Jan. 2023 (IEEE manuscript) M. Alioto, \u201cEditorial on the Opening of the 2022 TVLSI Editorial Year \u2013 Connecting Trends from Society to VLSI […]<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"nf_dc_page":"","om_disable_all_campaigns":false,"footnotes":""},"class_list":["post-30","page","type-page","status-publish","hentry"],"jetpack_sharing_enabled":true,"_links":{"self":[{"href":"https:\/\/www.green-ic.org\/wp-json\/wp\/v2\/pages\/30","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.green-ic.org\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.green-ic.org\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.green-ic.org\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.green-ic.org\/wp-json\/wp\/v2\/comments?post=30"}],"version-history":[{"count":5,"href":"https:\/\/www.green-ic.org\/wp-json\/wp\/v2\/pages\/30\/revisions"}],"predecessor-version":[{"id":3382,"href":"https:\/\/www.green-ic.org\/wp-json\/wp\/v2\/pages\/30\/revisions\/3382"}],"wp:attachment":[{"href":"https:\/\/www.green-ic.org\/wp-json\/wp\/v2\/media?parent=30"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}