1 | S. Jain, L. Lin, M. Alioto, Adaptive Digital Circuits for Power-Performance Range beyond Wide Voltage Scaling, Springer, 2020 |
2 | A. Alvarez, G. Ponnusamy, M. Alioto, “Energy-Quality Scalable Memory-Frugal Feature Extraction for Always-On Deep Sub-mW Distributed Vision,” IEEE Access, vol. 8, pp. 18951-18961, Jan. 2020 |
3 | S. Jain, L. Longyang, M. Alioto, “Automated Design of Reconfigurable Micro-Architectures for Accelerators under Wide Voltage Scaling,” IEEE Trans. on VLSI Systems, vol. 28, no. 3, pp. 777-790, March 2020 |
4 | J. H. Teo, S. Cheng, M. Alioto, “Low-Energy Voice Activity Detection via Energy-Quality Scaling from Data Conversion to Machine Learning,” IEEE Trans. on CAS – part I, vol. 67, no. 4, pp. 1378-1377, April 2020 |
5 | O. Aiello, P. Crovetti, M. Alioto, “Fully Synthesizable Low-Area Analogue-to-Digital Converters with Minimal Design Effort Based on the Dyadic Digital Pulse Modulation,” IEEE Access, vol. 8, pp. 70890-70899, April 2020 |
6 | S. Jain, L. Lin, M. Alioto, “Broad-Purpose In-Memory Computing for Signal Monitoring and Machine Learning Workloads,” IEEE Solid-State Circuits Letters (invited), vol. 3, pp. 394-397, Sept. 2020 |
7 | P. Toledo, P. Crovetti, O. Aiello, M. Alioto, “Fully Digital Rail-to-Rail OTA with Sub-1,000 µm2 Area, 250-mV Minimum Supply and nW Power at 150-pF Load in 180nm,” IEEE Solid-State Circuits Letters, vol. 3, pp. 474-477, Sept. 2020 |
8 | S. Jain, L. Lin, M. Alioto, “Processor Energy-Performance Range Extension Beyond Voltage Scaling via Drop-In Methodologies,” IEEE Journal of Solid-State Circuits (invited), vol. 55, no. 10, pp. 2670-2679, Oct. 2020 |
9 | L. Lin, S. Jain, M. Alioto, “Sub-nW Microcontroller with Dual-Mode Logic and Self-startup for Battery-Indifferent Sensor Nodes,” accepted to IEEE JSSC |
10 | L. Fassio, F. Settino, L. Longyang, R. De Rose, M. Lanuzza, F. Crupi, M. Alioto, “A Robust Sub-Threshold, Low Power-Delay, Energy and Area Efficient Level Shifter,” accepted to IEEE TCAS-II |
11 | O. Aiello, P. Crovetti, P. Toledo, M. Alioto, “Rail-to-Rail Dynamic Voltage Comparator Scalable down to pW-Range Power and 0.15-V Supply,” accepted to IEEE Trans. on Circuits and Systems – part II |
12 | U. De Alwis, M. Alioto, “TempDiff: Feature Map-Level CNN Sparsity Enhancement at Near-Zero Memory Overhead via Temporal Difference,” IEEE JETCAS, vol. 11, no. 4, pp. 620-633, Dec. 2021 |
13 | V. Konandur Rajanna, M. Alioto, “On-Chip Links with Energy-Quality Tradeoff in Error-Resilient and Machine Learning Applications,” accepted to IEEE Journal of Solid-State Circuits |
14 | S. Jain, L. Lin, M. Alioto, “±CIM SRAM for Signed In-Memory Broad-Purpose Computing from DSP to Neural Processing,” accepted to IEEE Journal of Solid-State Circuits (invited) |
15 | A Multi-Mode Multi-Coil Coupled Tuned Inductive Peaking ILFD for Low Injected Power With Compact Size |
16 | Design of Reconfigurable dB-Linear Variable-Gain Amplifier and Switchable-Order Gm-C Filter in 65-nm CMOS Technology |
17 | Design of a wideband variable-gain amplifier with self-compensated transistor for accurate dB-linear characteristic in 65 nm CMOS technology |
18 | Design of Differential Variable-Gain Transimpedance Amplifier in 0.18-µm SiGe BiCMOS |
19 | Ka-Band Marchand Balun with Edge and Broadside Coupled Configuration |
20 | Design of a Ka-Band U-Shaped Bandpass Filter with 20-GHz Bandwidth in 0.13-μm BiCMOS Technology |
21 | A 60 GHz 8-Way Combined Power Amplifier in 0.18 μm SiGe BiCMOS |
22 | A Two-Stage X-Band 20.7-dBm Power Amplifier in 40-nm CMOS Technology |
23 | A Monolithically Integrated Single-Input Load-Modulated Balanced Amplifier with Enhanced Efficiency at Power Back-Off |
24 | Neural Epitome Search for Architecture-Agnostic Network Compression |
25 | T.-N. Pham, Q.-K. Trinh, I.-J. Chang, M. Alioto, “STT-BNN: A Novel STT-MRAM In-Memory Computing Macro for Binary Neural Networks,” IEEE JETCAS, vol. 12, no. 2, pp. 569-579, June 2022T.-N. Pham, Q.-K. Trinh, I.-J. Chang, M. Alioto, “STT-BNN: A Novel STT-MRAM In-Memory Computing Macro for Binary Neural Networks,” IEEE JETCAS, vol. 12, no. 2, pp. 569-579, June 2022 |
26 | Distributed Anomaly Detection in Smart Grids: A Federated Learning-Based Approach |
27 | K. Ali, J. H. Teo, S. Sarkar, M. Alioto, “Dual-Mode Conversion Gating, Comparator Merging and Reference-Less Calibration for 2.7X Energy Reduction in SAR ADCs under Low-Activity Inputs,” in print on IEEE Solid-State Circuits Letters |
28 | A Linear-in-Decibel Automatic Gain Control Amplifier With Dual Mode Continuous Gain Tuning |
29 | A Fully Integrated Pulling Mitigation Synthesizer for NB-IoT Transmitter |