Videos
Publications
| 1 | F. Berti, S. Bhasin, J. Breier, Xiaolu Hou, R. Poussier, F.-X. Standaert, B. Udvarhelyi, A Finer-Grain Analysis of the Leakage (Non) Resilience of OCB, to appear in IACR Transactions on Cryptographic Hardware and Embedded Systems 2022 |
| 2 | Breier, Jakub, Dirmanto Jap, Xiaolu Hou, and Shivam Bhasin. “On Side Channel Vulnerabilities of Bit Permutations in Cryptographic Algorithms.” IEEE Transactions on Information Forensics and Security (2019) |
| 3 | Bhasin, Shivam, Jakub Breier, Xiaolu Hou, Dirmanto Jap, Romain Poussier, and Siang Meng Sim. “SITM: See-In-The-Middle Side-Channel Assisted Middle Round Differential Cryptanalysis on SPN Block Ciphers.” IACR Transactions on Cryptographic Hardware and Embedded Systems (2020): 95-122. |
| 4 | Alam, Manaar, Arnab Bag, Debapriya Basu Roy, Dirmanto Jap, Jakub Breier, Shivam Bhasin, and Debdeep Mukhopadhyay. “Neural Network-based Inherently Fault-tolerant Hardware Cryptographic Primitives without Explicit Redundancy Checks.” ACM Journal on Emerging Technologies in Computing Systems (JETC) 17, no. 1 (2020): 1-30. |
| 5 | Kumar, Vinay BY, Suman Deb, Naina Gupta, Shivam Bhasin, Jawad Haj-Yahya, Anupam Chattopadhyay, and Avi Mendelson. “Towards Designing a Secure RISC-V System-on-Chip: ITUS.” Journal of Hardware and Systems Security 4, no. 4 (2020): 329-342. |
| 6 | Breier, Jakub, Dirmanto Jap, Xiaolu Hou, Shivam Bhasin, and Yang Liu. “SNIFF: reverse engineering of neural networks with fault attacks.” IEEE Transactions on Reliability (2021). |
| 7 | Hou, X., Breier, J., & Bhasin, S. (2022). SBCMA: Semi-Blind Combined Middle-Round Attack on Bit-Permutation Ciphers With Application to AEAD Schemes. IEEE Transactions on Information Forensics and Security, 17, 3677-3690. |
| 8 | Ravi, P., Yang, B., Bhasin, S., Zhang, F., & Chattopadhyay, A. (2023). Fiddling the Twiddle Constants-Fault Injection Analysis of the Number Theoretic Transform. IACR Transactions on Cryptographic Hardware and Embedded Systems, 447-481. |
| 9 | Picek, S., Heuser, A., Jovic, A., Bhasin, S., & Regazzoni, F. (2023). Tipping the Balance: Imbalanced Classes in Deep Learning Side-channel Analysis. IEEE Design & Test. |
| 10 | Bagheri, N., Sadeghi, S., Ravi, P., Bhasin, S., & Soleimany, H. (2022). SIPFA: statistical ineffective persistent faults analysis on Feistel ciphers. IACR Transactions on Cryptographic Hardware and Embedded Systems, 367-390. |
| 11 | invited paper: M. Alioto, “Trends in Hardware Security: from Basics to ASICs,” IEEE Solid-State Circuits Magazine (invited), vol. 11, no. 3, pp. 56-74, Aug. 2019 |
| 12 | S. Taneja, M. Alioto, “Fully-Synthesizable All-Digital Unified Dynamic Entropy Generation, Extraction and Utilization within the Same Cryptographic Core,” IEEE Solid-State Circuits Letters (invited), vol. 3, pp. 402-405, Sept. 2020 |
| 13 | A Power-Aware Toggling-Frequency Actuator in Data-Toggling SRAM for Secure Data Protection |
| 14 | Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic AES: Design, Countermeasures and Evaluation |
| 15 | A Novel Normalized Variance-Based Differential Power Analysis Against Masking Countermeasures |
| 16 | “PQC Acceleration Using GPUs: FrodoKEM, NewHope, and Kyber” |
| 17 | INVITED PAPER: S. Taneja, V. Konandur Rajanna, M. Alioto, “In-Memory Unified TRNG and Multi-Bit PUF for Ubiquitous Hardware Security,” IEEE Journal of Solid-State Circuits (invited), vol. 57, no. 1, pp. 153-166, Jan. 2022 |
| 18 | “MemEnc: A Lightweight, Low-Power, and Transparent Memory Encryption Engine for IoT” |
| 19 | “Protecting Network-on-Chip Intellectual Property using Timing Channel Fingerprinting” |
| 20 | A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic AES Accelerator Against Side-Channel Attacks |
| 21 | Bagheri, N., Sadeghi, S., Ravi, P., Bhasin, S., & Soleimany, H. (2022). SIPFA: Statistical Ineffective Persistent Faults Analysis on Feistel Ciphers. IACR Transactions on Cryptographic Hardware and Embedded Systems, 367-390. |
| 22 | “S. Taneja, M. Alioto, “”Run-Time PUF Adaptation for Resilient and Energy-Efficient Key Generation via Sensor Fusion and Machine Learning,”” accepted to JSSC “ |
| 23 | M. Alioto, “Aggressive Design Reuse for Ubiquitous Zero-Trust Edge Security – From Physical Design to Machine Learning-Based Hardware Patching,” IEEE Open Journal of the Solid-State Circuits Society (invited), vol. 3, pp. 1-16, 2023 |
| 24 | Laser Voltage Probing Attack Detection with 100% Area/Time Coverage at Above/Below the Bandgap Wavelength and Fully-Automated Design |
| 25 | AI Attacks AI: Recovering Neural Network architecture from NVDLA using AI-assisted Side Channel Attack |
| 26 | S. Taneja, M. Alioto, Immersed-in-logic and in-memory primitives for ubiquitous hardware security, Springer, 2024 |
Presentations
| 1 | invited paper at CICC 2019: M. Alioto, S. Taneja, “Enabling Ubiquitous Hardware Security via Energy-Efficient Primitives and Systems,” in Proc. of IEEE CICC 2019 (invited), Austin (USA), April 2019 |
| 2 | ITUS: A Secure RISC-V System-on-Chip |
| 3 | Reconfigurable Routing Paths As Noise Generators Using NoC Platform for Hardware Security Applications””, Ho Weng-Geng, Pammu Ali Akbar, Lwin Ne Kyaw Zwa, Chong Kwen-Siong, Gwee Bah-Hwee |
| 4 | Batina, Lejla, Shivam Bhasin, Dirmanto Jap, and Stjepan Picek. “Poster: Recovering the Input of Neural Networks via Single Shot Side-channel Attacks.” In Proceedings of the 2019 ACM SIGSAC Conference on Computer and Communications Security, pp. 2657-2659. 2019. |
| 5 | Recruiting Fault Tolerance Techniques for Microprocessor Security |
| 6 | Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic AES Accelerator Based on Standard Library Cells””, Chong Kwen-Siong, Shreedhar Aparna, Lwin Ne Kyaw Zwa, Kyaw Nay Aung, Ho Weng-Geng, Wang Chao, Zhou Jun, Gwee Bah-Hwee, Chang Joseph S. |
| 7 | Vinay BY Kumar, Suman D, Rupesh K, Mustafa K, Anupam Chattopadhyay, Avi Mendelson: “Recruiting Fault Tolerance Techniques for Microprocessor Security”, 28th IEEE Asian Test Symposium (ATS), 2019, Kolkata |
| 8 | Security in the Post-Quantum Era: Threats and Countermeasures – Beyond Post-Quantum Security |
| 9 | Vinay BY Kumar, Naina Gupta, Anupam Chattopadhyay, Michael Kasper, Christoph Krauss and Ruben Niederhagen: “Post-Quantum Secure Boot”, Design, Automation and Test in Europe Conference (DATE), 2020, Grenoble |
| 10 | Bhasin, Shivam, Trevor E. Carlson, Anupam Chattopadhyay, Vinay BY Kumar, Avi Mendelson, Romain Poussier, and Yaswanth Tavva. “Secure Your SoC: Building System-on-Chip Designs for Security.” Published at IEEE SOCC 2020 |
| 11 | S. Taneja, M. Alioto, “Deep Sub-pJ/bit Low-Area Energy-Security Scalable SIMON Crypto-Core,” accepted to IEEE ISCAS 2020, Seville (Spain), Oct 2020 |
| 12 | A Highly Efficient Power Model for Correlation Power Analysis (CPA) of Pipelined Advanced Encryption Standard (AES)””, Ng Jun-Sheng, Chen Juncheng, Kyaw Nay Aung, Lwin Ne Kyaw Zwa, Ho Weng-Geng, Chong Kwen-Siong, Gwee Bah-Hwee |
| 13 | A DPA-Resistant Asynchronous-Logic NoC Router with Dual-Supply-Voltage-Scaling for Multicore Cryptographic Applications””, Ho Weng-Geng, Lwin Ne Kyaw Zwa, Kyaw Nay Aung, Ng Jun-Sheng, Chen Juncheng, Chong Kwen-Siong, Gwee Bah-Hwee, Chang, Joseph S |
| 14 | Jap, Dirmanto, and Shivam Bhasin. “Practical Reverse Engineering of Secret Sboxes by Side-Channel Analysis.” In 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5. IEEE, 2020. |
| 15 | High Throughput and Secure Authentication-Encryption on Asynchronous Multicore Processor for Edge Computing IoT Applications””, Ho Weng-Geng, Pammu Ali Akbar, Lwin Ne Kyaw Zwa, Chong Kwen-Siong, Gwee Bah-Hwee |
| 16 | S. Taneja, M. Alioto, “”Fully-Synthesizable All-Digital Unified Dynamic Entropy Generation, Extraction and Utilization in a Cryptographic Core for Constrained Secure Systems,”” ASSC 2020 |
| 17 | Laser Attack Benchmark Suite |
| 18 | High Efficiency Early-Complete Brute Force Elimination Method for Security Analysis of Camouflage IC |
| 19 | Azouaoui, Melissa, François Durvaux, Romain Poussier, François-Xavier Standaert, Kostas Papagiannopoulos, and Vincent Verneuil. “On the Worst-Case Side-Channel Security of ECC Point Randomization in Embedded Devices.” In International Conference on Cryptology in India, pp. 205-227. Springer, Cham, 2020 |
| 20 | Ravi, Prasanna, Romain Poussier, Shivam Bhasin, and Anupam Chattopadhyay. “On Configurable SCA Countermeasures Against Single Trace Attacks for the NTT.” In International Conference on Security, Privacy, and Applied Cryptography Engineering, pp. 123-146. Springer, Cham, 2020. |
| 21 | S. Taneja, V. Konandur, M. Alioto, “Unified In-Memory Dynamic (TRNG) and Multi-Bit Static (PUF) Entropy Generation for Ubiquitous Hardware Security,” accepted to ISSCC 2021 |
| 22 | Hou, Xiaolu, Jakub Breier, and Shivam Bhasin. “DNFA: Differential no-fault analysis of bit permutation based ciphers assisted by side-channel.” In 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 182-187. IEEE, 2021 |
| 23 | Normalized Differential Power Analysis – A Ghost Peak Suppressing Differential Power Analysis |
| 24 | Q. Fang, M. Alioto, “Last-round and Joint First/Last-Round Power Analysis Attacks on PRESENT,” accepted to IEEE AsianHOST 2021 |
| 25 | Q. Fang, L. Lin, Y. Z. Wong, H. Zhang, M. Alioto, “Side-Channel Attack Counteraction via Machine Learning Targeted Power Compensation for Post-Silicon HW Security Patching,” accepted to ISSCC 2022 |
| 26 | Sentry-NoC: A Statically Scheduled NoC for Secure SoCs |
| 27 | Saha, Sayandeep, et al. “Divided We Stand, United We Fall: Security Analysis of Some SCA+ SIFA Countermeasures Against SCA-Enhanced Fault Template Attacks.” To Appear in Asiacrypt 2021. |
| 28 | On Threat of Hardware Trojan to Post-Quantum Lattice-Based Schemes: A Key Recovery Attack on SABER and Beyond |
| 29 | Robustness Against Adversarial Attacks using Dimensionality |
| 30 | ROWBACK: Robust Watermarking for neural networks using BACKdoors |
| 31 | V. Konandur, H. Raghav, T. Wang, M. Alioto, “Fully-Digital Broadband Calibration-Less Impedance Monitor for Probe Insertion Detection against Power Analysis Attacks,” in Proc. of VLSI Symposium 2022, Honolulu (USA), June 2022, pp. 140-141 |
| 32 | Non-profiling Based Correlation Optimization Deep Learning Analysis |
| 33 | An Asynchronous-Logic Masked Advanced Encryption Standard (AES) Accelerator and its Side-Channel Attack Evaluations |
| 34 | H. Zhang, L. Lin, Q. Fang, M. Alioto, “On-Chip Laser Voltage Probing Attack Detection with 100% Area Coverage at Above/Below the Bandgap Wavelength and Fully-Automated Design,” in Proc. of VLSI Symposium 2022, Honolulu (USA), June 2022, pp. 144-145 |
| 35 | ROFL: RObust privacy preserving Federated Learning |
| 36 | Elasticlave: An Efficient Memory Model for Enclaves |
| 37 | Fast, Robust and Accurate Detection of Cache-based Spectre Attack Phases |
| 38 | Khairallah, Mustafa, and Shivam Bhasin. “Hardware Implementation of Masked SKINNY SBox with Application to AEAD.” In Security, Privacy, and Applied Cryptography Engineering: 12th International Conference, SPACE 2022, Jaipur, India, December 9–12, 2022, Proceedings, pp. 50-69. Cham: Springer Nature Switzerland, 2022. |
| 39 | Incremental Linear Regression Attack |
| 40 | Leaking Control Flow Information via the Hardware Prefetcher |
| 41 | A Next-Generation Side-Channel Detector for General-Purpose Processors |
| 42 | A Privacy-Preserving Protocol Level Approach to Prevent Machine Learning Modelling Attacks on PUFs in the Presence of Semi-Honest Verifiers |
| 43 | J. Basu, Sachin Taneja, V. Konandur Rajanna, T. Wang, M. Alioto, “ECC-Less Multi-Level SRAM Physically Unclonable Function and 127% PUF-to-Memory Capacity Ratio with No Bitcell Modification in 28nm,” in Proc. of VLSI Symposium 2023, Kyoto (Japan), June 2023 |
| 44 | H. Zhang, L. Lin, Q. Fang, U. S. H. Kalingage, M. Alioto, “Self-Referenced Design-Agnostic Laser Voltage Probing Attack Detection with 100% Protection Coverage, 58% Area Overhead for Automated Design,” in Proc. of VLSI Symposium 2023, Kyoto (Japan), June 2023 |
| 45 | Q. Fang, L. Lin, H. Zhang, T. Wang, M. Alioto, “Voltage Scaling-Agnostic Counteraction of Side-Channel Neural Net Reverse Engineering via Machine Learning Compensation and Multi-Level Shuffling,” in Proc. of VLSI Symposium 2023, Kyoto (Japan), June 2023 |
| 46 | Saha, S., Ravi, P., Jap, D., & Bhasin, S. (2023, April). Non-Profiled Side-Channel Assisted Fault Attack: A Case Study on DOMREP. In 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE) (pp. 1-6). IEEE. |
| 47 | Beegala, P., Roy, D. B., Ravi, P., Bhasin, S., Chattopadhyay, A., & Mukhopadhyay, D. (2022, October). Efficient Loop Abort Fault Attacks on Supersingular Isogeny based Key Exchange (SIKE). In 2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)(pp. 1-6). IEEE. |
| 48 | A RISC-V SoC with Hardware Trojans: Case Study on Trojan-ing the On-Chip Protocol Conversion |
| 49 | CRYSTALS-Dilithium on RISC-V Processor: Lightweight Secure Boot Using Post-Quantum Digital Signature |
| 50 | Improving FPGA-based Async-logic AES Accelerator with the Integration of Sync-logic Block RAMs |
| 51 | A Residual-Remainder Coupled Unlimited Sampling Framework for High Dynamic Range Signal Conversion |
| 52 | Non-profiling Time-Frequency Analysis based Correlation Optimization with Deep Learning |
| 53 | A Novel Non-profiling Side-Channel Attack on Masked Devices with Connectivity Matrix |
| 54 | Y. Chen, A. Hajiabadi, and T. E. Carlson, “GadgetSpinner: A New Transient Execution Primitive using the Loop Stream Detector,” International Symposium on High-Performance Computer Architecture (HPCA), 2024. |
| 55 | B. Amornpaisannon, A. Diavastos, L. -S. Peh and T. E. Carlson, “Secure Run-Time Hardware Trojan Detection Using Lightweight Analytical Models,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 43, no. 2, pp. 431-441, Feb. 2024, doi: 10.1109/TCAD.2023.3316113 |
| 56 | A. Pashrashid, A. Hajiabadi, and T. E. Carlson, “HidFix: Efficient Mitigation of Cache-based Spectre Attacks Through Hidden Rollbacks,” International Conference on Computer-Aided Design (ICCAD), 2023. |
| 57 | Y. Chen, L. Pei, and T. E. Carlson, “AfterImage: Leaking Control Flow Data and Tracking Load Operations via the Hardware Prefetcher,” International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2023 |
| 58 | Ayanga Imesha Kumari Kalupahana, Ananta Narayanan Balaji, Xiaokui Xiao, and Li-Shiuan Peh. 2023. SeRaNDiP: Leveraging Inherent Sensor Random Noise for Differential Privacy Preservation in Wearable Community Sensing Applications. Proc. ACM Interact. Mob. Wearable Ubiquitous Technol. 7, 2, Article 61 (June 2023), 38 pages |
| 59 | SRAM PUF Extracting Entropy from Every Bitcell Transistor for 6 bit/bitcell with Data Fingerprinting Capability and Native Cryptography-Grade Entropy |
| 60 | Y. Chen, A. Hajiabadi, L. Pei, and T. E. Carlson, “PrefetchX: Cross-Core Cache-Agnostic Prefetcher-Based Side-Channel Attacks” |
| 61 | Y. Chen, A. Pashrashid, Y. Wu, and T. E. Carlson, “Prime+Reset: Introducing A Novel Cross-World Covert-Channel Through Comprehensive Security Analysis on ARM TrustZone” |
Demos and public materials
PUFdb: http://www.green-ic.org/pufdb
HWsecdb: http://www.green-ic.org/hwsecdb